ARM: OMAP5: Enable arch timer support
Enable Cortex A15 generic timer support for OMAP5 based SOCs. The CPU local timers run on the free running real time counter clock. Acked-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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@ -33,9 +33,21 @@
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cpus {
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cpu@0 {
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compatible = "arm,cortex-a15";
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timer {
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compatible = "arm,armv7-timer";
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/* 14th PPI IRQ, active low level-sensitive */
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interrupts = <1 14 0x308>;
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clock-frequency = <6144000>;
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};
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};
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cpu@1 {
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compatible = "arm,cortex-a15";
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timer {
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compatible = "arm,armv7-timer";
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/* 14th PPI IRQ, active low level-sensitive */
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interrupts = <1 14 0x308>;
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clock-frequency = <6144000>;
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};
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};
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};
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@ -74,6 +74,7 @@ config SOC_OMAP5
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select HAVE_SMP
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select ARM_CPU_SUSPEND if PM
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select SOC_HAS_REALTIME_COUNTER
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select ARM_ARCH_TIMER
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comment "OMAP Core Type"
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depends on ARCH_OMAP2
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@ -41,6 +41,7 @@
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#include <plat/dmtimer.h>
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#include <asm/smp_twd.h>
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#include <asm/sched_clock.h>
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#include <asm/arch_timer.h>
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#include "common.h"
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#include <plat/omap_hwmod.h>
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#include <plat/omap_device.h>
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@ -488,9 +489,15 @@ OMAP_SYS_TIMER(4)
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#ifdef CONFIG_SOC_OMAP5
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static void __init omap5_timer_init(void)
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{
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int err;
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omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
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omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
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realtime_counter_init();
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err = arch_timer_of_register();
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if (err)
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pr_err("%s: arch_timer_register failed %d\n", __func__, err);
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}
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OMAP_SYS_TIMER(5)
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#endif
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