drm/amdgpu: Restore msix after FLR
After FLR, the msix will be cleared, so need to re-enable it. Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com> Signed-off-by: Emily.Deng <Emily.Deng@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -278,6 +278,21 @@ static bool amdgpu_msi_ok(struct amdgpu_device *adev)
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return true;
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return true;
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}
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}
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static void amdgpu_restore_msix(struct amdgpu_device *adev)
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{
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u16 ctrl;
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pci_read_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
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if (!(ctrl & PCI_MSIX_FLAGS_ENABLE))
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return;
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/* VF FLR */
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ctrl &= ~PCI_MSIX_FLAGS_ENABLE;
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pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl);
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ctrl |= PCI_MSIX_FLAGS_ENABLE;
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pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl);
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}
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/**
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/**
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* amdgpu_irq_init - initialize interrupt handling
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* amdgpu_irq_init - initialize interrupt handling
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*
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*
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@ -569,6 +584,9 @@ void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
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{
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{
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int i, j, k;
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int i, j, k;
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if (amdgpu_sriov_vf(adev))
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amdgpu_restore_msix(adev);
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for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
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for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
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if (!adev->irq.client[i].sources)
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if (!adev->irq.client[i].sources)
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continue;
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continue;
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