UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

pinctrl: renesas: r8a779g0: Add support for AVB/TSN power-sources 

Add support for configuring the I/O voltage levels of the Ethernet AVB
and Ethernet TSN pins on the R-Car V4H SoC.  "PIN_VDDQ_AVB[012]" and
"PIN_VDDQ_TSN0" can be configured for 1.8V or 2.5V operation.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c046e0be7d26302061d7aa629180a451734ddf8f.1678271030.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2023-03-08 11:42:44 +01:00
parent d04b961dd4
commit 3c2465067f
1 changed files with 36 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
drivers/pinctrl/renesas/pfc-r8a779g0.c
View File

@ -49,6 +49,12 @@
PORT_GP_CFG_21(7, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_21(7, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_14(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33) PORT_GP_CFG_14(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33)
#define CPU_ALL_NOGP(fn) \
PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \
PIN_NOGP_CFG(VDDQ_AVB1, "VDDQ_AVB1", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \
PIN_NOGP_CFG(VDDQ_AVB2, "VDDQ_AVB2", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \
PIN_NOGP_CFG(VDDQ_TSN0, "VDDQ_TSN0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25)
/* GPSR0 */ /* GPSR0 */
#define GPSR0_18 F_(MSIOF2_RXD, IP2SR0_11_8) #define GPSR0_18 F_(MSIOF2_RXD, IP2SR0_11_8)
#define GPSR0_17 F_(MSIOF2_SCK, IP2SR0_7_4) #define GPSR0_17 F_(MSIOF2_SCK, IP2SR0_7_4)
@ -1221,10 +1227,12 @@ static const u16 pinmux_data[] = {
*/ */
enum { enum {
GP_ASSIGN_LAST(), GP_ASSIGN_LAST(),
NOGP_ALL(),
}; };
static const struct sh_pfc_pin pinmux_pins[] = { static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(), PINMUX_GPIO_GP_ALL(),
PINMUX_NOGP_ALL(),
}; };
/* - AUDIO CLOCK ----------------------------------------- */ /* - AUDIO CLOCK ----------------------------------------- */
@ -3973,23 +3981,42 @@ static int r8a779g0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{ {
int bit = pin & 0x1f; int bit = pin & 0x1f;
*pocctrl = pinmux_ioctrl_regs[POC0].reg; switch (pin) {
if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 18)) case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 18):
*pocctrl = pinmux_ioctrl_regs[POC0].reg;
return bit; return bit;
*pocctrl = pinmux_ioctrl_regs[POC1].reg; case RCAR_GP_PIN(1, 0) ... RCAR_GP_PIN(1, 22):
if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 22)) *pocctrl = pinmux_ioctrl_regs[POC1].reg;
return bit; return bit;
*pocctrl = pinmux_ioctrl_regs[POC3].reg; case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 12):
if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 12)) *pocctrl = pinmux_ioctrl_regs[POC3].reg;
return bit; return bit;
*pocctrl = pinmux_ioctrl_regs[POC8].reg; case PIN_VDDQ_TSN0:
if (pin >= RCAR_GP_PIN(8, 0) && pin <= RCAR_GP_PIN(8, 13)) *pocctrl = pinmux_ioctrl_regs[POC4].reg;
return 0;
case PIN_VDDQ_AVB2:
*pocctrl = pinmux_ioctrl_regs[POC5].reg;
return 0;
case PIN_VDDQ_AVB1:
*pocctrl = pinmux_ioctrl_regs[POC6].reg;
return 0;
case PIN_VDDQ_AVB0:
*pocctrl = pinmux_ioctrl_regs[POC7].reg;
return 0;
case RCAR_GP_PIN(8, 0) ... RCAR_GP_PIN(8, 13):
*pocctrl = pinmux_ioctrl_regs[POC8].reg;
return bit; return bit;
return -EINVAL; default:
return -EINVAL;
}
} }
static const struct pinmux_bias_reg pinmux_bias_regs[] = { static const struct pinmux_bias_reg pinmux_bias_regs[] = {