drm/amd/display: Add DCN3 VPG
Video Package generator. used to prepare avi info, DP info etc Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Bhawanpreet Lakha
Alex Deucher
parent
73de3de5bc
commit
3c10f4fb90
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/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dc_bios_types.h"
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#include "dcn30_vpg.h"
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#include "reg_helper.h"
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#define DC_LOGGER \
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vpg3->base.ctx->logger
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#define REG(reg)\
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(vpg3->regs->reg)
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#undef FN
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#define FN(reg_name, field_name) \
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vpg3->vpg_shift->field_name, vpg3->vpg_mask->field_name
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#define CTX \
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vpg3->base.ctx
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static void vpg3_update_generic_info_packet(
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struct vpg *vpg,
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uint32_t packet_index,
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const struct dc_info_packet *info_packet)
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{
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struct dcn30_vpg *vpg3 = DCN30_VPG_FROM_VPG(vpg);
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uint32_t i;
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/* TODOFPGA Figure out a proper number for max_retries polling for lock
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* use 50 for now.
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*/
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uint32_t max_retries = 50;
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if (packet_index > 14)
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ASSERT(0);
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/* poll dig_update_lock is not locked -> asic internal signal
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* assume otg master lock will unlock it
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*/
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/* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
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* 0, 10, max_retries);
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*/
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/* TODO: Check if this is required */
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/* check if HW reading GSP memory */
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REG_WAIT(VPG_GENERIC_STATUS, VPG_GENERIC_CONFLICT_OCCURED,
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0, 10, max_retries);
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/* HW does is not reading GSP memory not reading too long ->
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* something wrong. clear GPS memory access and notify?
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* hw SW is writing to GSP memory
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*/
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REG_UPDATE(VPG_GENERIC_STATUS, VPG_GENERIC_CONFLICT_CLR, 1);
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/* choose which generic packet to use */
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REG_UPDATE(VPG_GENERIC_PACKET_ACCESS_CTRL,
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VPG_GENERIC_DATA_INDEX, packet_index*9);
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/* write generic packet header
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* (4th byte is for GENERIC0 only)
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*/
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REG_SET_4(VPG_GENERIC_PACKET_DATA, 0,
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VPG_GENERIC_DATA_BYTE0, info_packet->hb0,
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VPG_GENERIC_DATA_BYTE1, info_packet->hb1,
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VPG_GENERIC_DATA_BYTE2, info_packet->hb2,
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VPG_GENERIC_DATA_BYTE3, info_packet->hb3);
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/* write generic packet contents
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* (we never use last 4 bytes)
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* there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers
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*/
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{
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const uint32_t *content =
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(const uint32_t *) &info_packet->sb[0];
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for (i = 0; i < 8; i++) {
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REG_WRITE(VPG_GENERIC_PACKET_DATA, *content++);
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}
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}
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/* atomically update double-buffered GENERIC0 registers in frame mode
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* (update at next block_update when block_update_lock == 0).
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*/
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switch (packet_index) {
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case 0:
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REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
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VPG_GENERIC0_FRAME_UPDATE, 1);
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break;
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case 1:
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REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
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VPG_GENERIC1_FRAME_UPDATE, 1);
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break;
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case 2:
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REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
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VPG_GENERIC2_FRAME_UPDATE, 1);
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break;
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case 3:
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REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
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VPG_GENERIC3_FRAME_UPDATE, 1);
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break;
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case 4:
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REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
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VPG_GENERIC4_FRAME_UPDATE, 1);
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break;
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case 5:
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REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
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VPG_GENERIC5_FRAME_UPDATE, 1);
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break;
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case 6:
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REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
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VPG_GENERIC6_FRAME_UPDATE, 1);
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break;
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case 7:
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REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
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VPG_GENERIC7_FRAME_UPDATE, 1);
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break;
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case 8:
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REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
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VPG_GENERIC8_FRAME_UPDATE, 1);
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break;
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case 9:
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REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
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VPG_GENERIC9_FRAME_UPDATE, 1);
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break;
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case 10:
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REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
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VPG_GENERIC10_FRAME_UPDATE, 1);
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break;
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case 11:
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REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
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VPG_GENERIC11_FRAME_UPDATE, 1);
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break;
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case 12:
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REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
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VPG_GENERIC12_FRAME_UPDATE, 1);
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break;
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case 13:
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REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
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VPG_GENERIC13_FRAME_UPDATE, 1);
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break;
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case 14:
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REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
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VPG_GENERIC14_FRAME_UPDATE, 1);
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break;
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default:
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break;
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}
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}
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static struct vpg_funcs dcn30_vpg_funcs = {
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.update_generic_info_packet = vpg3_update_generic_info_packet,
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};
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void vpg3_construct(struct dcn30_vpg *vpg3,
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struct dc_context *ctx,
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uint32_t inst,
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const struct dcn30_vpg_registers *vpg_regs,
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const struct dcn30_vpg_shift *vpg_shift,
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const struct dcn30_vpg_mask *vpg_mask)
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{
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vpg3->base.ctx = ctx;
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vpg3->base.inst = inst;
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vpg3->base.funcs = &dcn30_vpg_funcs;
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vpg3->regs = vpg_regs;
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vpg3->vpg_shift = vpg_shift;
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vpg3->vpg_mask = vpg_mask;
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}
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@ -0,0 +1,133 @@
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/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DAL_DCN30_VPG_H__
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#define __DAL_DCN30_VPG_H__
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#define DCN30_VPG_FROM_VPG(vpg)\
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container_of(vpg, struct dcn30_vpg, base)
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#define VPG_DCN3_REG_LIST(id) \
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SRI(VPG_GENERIC_STATUS, VPG, id), \
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SRI(VPG_GENERIC_PACKET_ACCESS_CTRL, VPG, id), \
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SRI(VPG_GENERIC_PACKET_DATA, VPG, id), \
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SRI(VPG_GSP_FRAME_UPDATE_CTRL, VPG, id)
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struct dcn30_vpg_registers {
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uint32_t VPG_GENERIC_STATUS;
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uint32_t VPG_GENERIC_PACKET_ACCESS_CTRL;
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uint32_t VPG_GENERIC_PACKET_DATA;
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uint32_t VPG_GSP_FRAME_UPDATE_CTRL;
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};
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#define DCN3_VPG_MASK_SH_LIST(mask_sh)\
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SE_SF(VPG0_VPG_GENERIC_STATUS, VPG_GENERIC_CONFLICT_OCCURED, mask_sh),\
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SE_SF(VPG0_VPG_GENERIC_STATUS, VPG_GENERIC_CONFLICT_CLR, mask_sh),\
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SE_SF(VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL, VPG_GENERIC_DATA_INDEX, mask_sh),\
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SE_SF(VPG0_VPG_GENERIC_PACKET_DATA, VPG_GENERIC_DATA_BYTE0, mask_sh),\
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SE_SF(VPG0_VPG_GENERIC_PACKET_DATA, VPG_GENERIC_DATA_BYTE1, mask_sh),\
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SE_SF(VPG0_VPG_GENERIC_PACKET_DATA, VPG_GENERIC_DATA_BYTE2, mask_sh),\
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SE_SF(VPG0_VPG_GENERIC_PACKET_DATA, VPG_GENERIC_DATA_BYTE3, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC0_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC1_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC2_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC3_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC4_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC5_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC6_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC7_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC8_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC9_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC10_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC11_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC12_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC13_FRAME_UPDATE, mask_sh),\
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SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC14_FRAME_UPDATE, mask_sh)
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#define VPG_DCN3_REG_FIELD_LIST(type) \
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type VPG_GENERIC_CONFLICT_OCCURED;\
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type VPG_GENERIC_CONFLICT_CLR;\
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type VPG_GENERIC_DATA_INDEX;\
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type VPG_GENERIC_DATA_BYTE0;\
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type VPG_GENERIC_DATA_BYTE1;\
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type VPG_GENERIC_DATA_BYTE2;\
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type VPG_GENERIC_DATA_BYTE3;\
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type VPG_GENERIC0_FRAME_UPDATE;\
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type VPG_GENERIC1_FRAME_UPDATE;\
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type VPG_GENERIC2_FRAME_UPDATE;\
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type VPG_GENERIC3_FRAME_UPDATE;\
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type VPG_GENERIC4_FRAME_UPDATE;\
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type VPG_GENERIC5_FRAME_UPDATE;\
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type VPG_GENERIC6_FRAME_UPDATE;\
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type VPG_GENERIC7_FRAME_UPDATE;\
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type VPG_GENERIC8_FRAME_UPDATE;\
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type VPG_GENERIC9_FRAME_UPDATE;\
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type VPG_GENERIC10_FRAME_UPDATE;\
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type VPG_GENERIC11_FRAME_UPDATE;\
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type VPG_GENERIC12_FRAME_UPDATE;\
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type VPG_GENERIC13_FRAME_UPDATE;\
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type VPG_GENERIC14_FRAME_UPDATE
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struct dcn30_vpg_shift {
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VPG_DCN3_REG_FIELD_LIST(uint8_t);
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};
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struct dcn30_vpg_mask {
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VPG_DCN3_REG_FIELD_LIST(uint32_t);
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};
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struct vpg;
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struct vpg_funcs {
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void (*update_generic_info_packet)(
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struct vpg *vpg,
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uint32_t packet_index,
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const struct dc_info_packet *info_packet);
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};
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struct vpg {
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const struct vpg_funcs *funcs;
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struct dc_context *ctx;
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int inst;
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};
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struct dcn30_vpg {
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struct vpg base;
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const struct dcn30_vpg_registers *regs;
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const struct dcn30_vpg_shift *vpg_shift;
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const struct dcn30_vpg_mask *vpg_mask;
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};
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void vpg3_construct(struct dcn30_vpg *vpg3,
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struct dc_context *ctx,
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uint32_t inst,
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const struct dcn30_vpg_registers *vpg_regs,
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const struct dcn30_vpg_shift *vpg_shift,
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const struct dcn30_vpg_mask *vpg_mask);
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#endif
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