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net: ethernet: mtk_eth_soc: use iopoll.h macro for DMA init 

Replace a tight busy-wait loop without a pause with a standard
readx_poll_timeout_atomic routine with a 5 us poll period.

Tested by booting a MT7621 device to ensure the driver initializes
properly.

Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Ilya Lipnitskiy 2021-04-22 22:21:08 -07:00 committed by David S. Miller
parent fa817272c3
commit 3bc8e0aff2
2 changed files with 14 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
drivers/net/ethernet/mediatek/mtk_eth_soc.c
View File

@ -2033,25 +2033,22 @@ static int mtk_set_features(struct net_device *dev, netdev_features_t features)
/* wait for DMA to finish whatever it is doing before we start using it again */ /* wait for DMA to finish whatever it is doing before we start using it again */
static int mtk_dma_busy_wait(struct mtk_eth *eth) static int mtk_dma_busy_wait(struct mtk_eth *eth)
{ {
unsigned long t_start = jiffies; unsigned int reg;
int ret;
u32 val;
while (1) { if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { reg = MTK_QDMA_GLO_CFG;
if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) & else
(MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) reg = MTK_PDMA_GLO_CFG;
return 0;
} else {
if (!(mtk_r32(eth, MTK_PDMA_GLO_CFG) &
(MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
return 0;
}
if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT)) ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val,
break; !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)),
} 5, MTK_DMA_BUSY_TIMEOUT_US);
if (ret)
dev_err(eth->dev, "DMA init timeout\n");
dev_err(eth->dev, "DMA init timeout\n"); return ret;
return -1;
} }
static int mtk_dma_init(struct mtk_eth *eth) static int mtk_dma_init(struct mtk_eth *eth)

2
drivers/net/ethernet/mediatek/mtk_eth_soc.h
View File

@ -214,7 +214,7 @@
#define MTK_TX_DMA_BUSY BIT(1) #define MTK_TX_DMA_BUSY BIT(1)
#define MTK_RX_DMA_EN BIT(2) #define MTK_RX_DMA_EN BIT(2)
#define MTK_TX_DMA_EN BIT(0) #define MTK_TX_DMA_EN BIT(0)
#define MTK_DMA_BUSY_TIMEOUT HZ #define MTK_DMA_BUSY_TIMEOUT_US 1000000
/* QDMA Reset Index Register */ /* QDMA Reset Index Register */
#define MTK_QDMA_RST_IDX 0x1A08 #define MTK_QDMA_RST_IDX 0x1A08