arm64/sysreg: Convert ID_AA64ZFR0_EL1 to automatic generation
Convert ID_AA64ZFR0_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-29-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
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@ -192,7 +192,6 @@
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#define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0)
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#define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1)
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#define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4)
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#define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0)
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#define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1)
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@ -737,28 +736,6 @@
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#define ID_AA64PFR1_MTE 0x2
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#define ID_AA64PFR1_MTE_ASYMM 0x3
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/* id_aa64zfr0 */
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#define ID_AA64ZFR0_EL1_F64MM_SHIFT 56
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#define ID_AA64ZFR0_EL1_F32MM_SHIFT 52
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#define ID_AA64ZFR0_EL1_I8MM_SHIFT 44
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#define ID_AA64ZFR0_EL1_SM4_SHIFT 40
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#define ID_AA64ZFR0_EL1_SHA3_SHIFT 32
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#define ID_AA64ZFR0_EL1_BF16_SHIFT 20
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#define ID_AA64ZFR0_EL1_BitPerm_SHIFT 16
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#define ID_AA64ZFR0_EL1_AES_SHIFT 4
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#define ID_AA64ZFR0_EL1_SVEver_SHIFT 0
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#define ID_AA64ZFR0_EL1_F64MM_IMP 0x1
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#define ID_AA64ZFR0_EL1_F32MM_IMP 0x1
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#define ID_AA64ZFR0_EL1_I8MM_IMP 0x1
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#define ID_AA64ZFR0_EL1_BF16_IMP 0x1
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#define ID_AA64ZFR0_EL1_SM4_IMP 0x1
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#define ID_AA64ZFR0_EL1_SHA3_IMP 0x1
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#define ID_AA64ZFR0_EL1_BitPerm_IMP 0x1
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#define ID_AA64ZFR0_EL1_AES_IMP 0x1
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#define ID_AA64ZFR0_EL1_AES_PMULL128 0x2
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#define ID_AA64ZFR0_EL1_SVEver_SVE2 0x1
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/* id_aa64mmfr0 */
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#define ID_AA64MMFR0_ECV_SHIFT 60
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#define ID_AA64MMFR0_FGT_SHIFT 56
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@ -46,6 +46,52 @@
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# feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration
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# item ACCDATA) though it may be more taseful to do something else.
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Sysreg ID_AA64ZFR0_EL1 3 0 0 4 4
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Res0 63:60
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Enum 59:56 F64MM
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 55:52 F32MM
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0b0000 NI
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0b0001 IMP
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EndEnum
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Res0 51:48
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Enum 47:44 I8MM
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0b0000 NI
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0b0001 IMP
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EndEnum
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Enum 43:40 SM4
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0b0000 NI
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0b0001 IMP
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EndEnum
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Res0 39:36
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Enum 35:32 SHA3
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0b0000 NI
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0b0001 IMP
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EndEnum
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Res0 31:24
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Enum 23:20 BF16
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0b0000 NI
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0b0001 IMP
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0b0010 EBF16
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EndEnum
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Enum 19:16 BitPerm
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0b0000 NI
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0b0001 IMP
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EndEnum
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Res0 15:8
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Enum 7:4 AES
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0b0000 NI
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0b0001 IMP
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0b0010 PMULL128
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EndEnum
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Enum 3:0 SVEver
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0b0000 IMP
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0b0001 SVE2
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EndEnum
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EndSysreg
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Sysreg ID_AA64SMFR0_EL1 3 0 0 4 5
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Enum 63 FA64
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0b0 NI
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