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drm/i915 Move HAS_CSR definition to platform definition 

Moving all GPU features to the platform struct definition allows for
        - standard place when adding new features from new platforms
        - possible to see supported features when dumping struct
          definitions

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Carlos Santa 2016-08-17 12:30:42 -07:00 committed by Rodrigo Vivi
parent 2631034677
commit 3bacde1999
2 changed files with 7 additions and 1 deletions
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3
drivers/gpu/drm/i915/i915_drv.h
View File

@ -656,6 +656,7 @@ struct intel_csr {
func(has_fbc) sep \ func(has_fbc) sep \
func(has_psr) sep \ func(has_psr) sep \
func(has_runtime_pm) sep \ func(has_runtime_pm) sep \
func(has_csr) sep \
func(has_pipe_cxsr) sep \ func(has_pipe_cxsr) sep \
func(has_hotplug) sep \ func(has_hotplug) sep \
func(cursor_needs_physical) sep \ func(cursor_needs_physical) sep \
@ -2791,7 +2792,7 @@ struct drm_i915_cmd_table {
#define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
#define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) #define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
#define HAS_CSR(dev) (IS_GEN9(dev)) #define HAS_CSR(dev) (INTEL_INFO(dev)->has_csr)
/* /*
* For now, anything with a GuC requires uCode loading, and then supports * For now, anything with a GuC requires uCode loading, and then supports

5
drivers/gpu/drm/i915/i915_pci.c
View File

@ -301,12 +301,14 @@ static const struct intel_device_info intel_skylake_info = {
BDW_FEATURES, BDW_FEATURES,
.is_skylake = 1, .is_skylake = 1,
.gen = 9, .gen = 9,
.has_csr = 1,
}; };
static const struct intel_device_info intel_skylake_gt3_info = { static const struct intel_device_info intel_skylake_gt3_info = {
BDW_FEATURES, BDW_FEATURES,
.is_skylake = 1, .is_skylake = 1,
.gen = 9, .gen = 9,
.has_csr = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
}; };
@ -321,6 +323,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_fbc = 1, .has_fbc = 1,
.has_runtime_pm = 1, .has_runtime_pm = 1,
.has_pooled_eu = 0, .has_pooled_eu = 0,
.has_csr = 1,
GEN_DEFAULT_PIPEOFFSETS, GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS, IVB_CURSOR_OFFSETS,
BDW_COLORS, BDW_COLORS,
@ -330,12 +333,14 @@ static const struct intel_device_info intel_kabylake_info = {
BDW_FEATURES, BDW_FEATURES,
.is_kabylake = 1, .is_kabylake = 1,
.gen = 9, .gen = 9,
.has_csr = 1,
}; };
static const struct intel_device_info intel_kabylake_gt3_info = { static const struct intel_device_info intel_kabylake_gt3_info = {
BDW_FEATURES, BDW_FEATURES,
.is_kabylake = 1, .is_kabylake = 1,
.gen = 9, .gen = 9,
.has_csr = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
}; };