pinctrl: rockchip: fix pull setting error for rk3399
This patch fixes the pinctrl pull bias setting, since the pull up/down setting is the contrary for gpio0(just the gpio0a and gpio0b) and gpio2(just the gpio2c and gpio2d). From the TRM said, the gpio0a pull polarity setting: gpio0a_p GPIO0A PE/PS programmation section, every GPIO bit corresponding to 2bits[PS:PE] 2'b00: Z(Normal operation); 2'b11: weak 1(pull-up); 2'b01: weak 0(pull-down); 2'b10: Z(Normal operation); Then, the other gpios setting as the following: gpio1a_p (e.g.: gpio1, gpio2a, gpio2b, gpio3...) GPIO1A PU/PD programmation section, every GPIO bit corresponding to 2bits 2'b00: Z(Normal operation); 2'b01: weak 1(pull-up); 2'b10: weak 0(pull-down); 2'b11: Z(Normal operation); For example,(rk3399evb board) sdmmc_cd --->gpio0_a7 localhost / # io -r -4 0xff320040 ff320040: 00004d5f In general,the value should be 0x0000cd5f since the pin has been set in the dts. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Cc: linux-gpio@vger.kernel.org Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
David Wu
Linus Walleij
parent
3beed93c16
commit
3ba6767a56
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@ -98,6 +98,15 @@ enum rockchip_pin_drv_type {
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DRV_TYPE_MAX
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};
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/**
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* enum type index corresponding to rockchip_pull_list arrays index.
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*/
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enum rockchip_pin_pull_type {
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PULL_TYPE_IO_DEFAULT = 0,
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PULL_TYPE_IO_1V8_ONLY,
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PULL_TYPE_MAX
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};
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/**
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* @drv_type: drive strength variant using rockchip_perpin_drv_type
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* @offset: if initialized to -1 it will be autocalculated, by specifying
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@ -123,6 +132,7 @@ struct rockchip_drv {
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* @bank_num: number of the bank, to account for holes
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* @iomux: array describing the 4 iomux sources of the bank
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* @drv: array describing the 4 drive strength sources of the bank
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* @pull_type: array describing the 4 pull type sources of the bank
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* @valid: are all necessary informations present
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* @of_node: dt node of this bank
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* @drvdata: common pinctrl basedata
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@ -143,6 +153,7 @@ struct rockchip_pin_bank {
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u8 bank_num;
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struct rockchip_iomux iomux[4];
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struct rockchip_drv drv[4];
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enum rockchip_pin_pull_type pull_type[4];
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bool valid;
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struct device_node *of_node;
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struct rockchip_pinctrl *drvdata;
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@ -198,6 +209,31 @@ struct rockchip_pin_bank {
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}, \
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}
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#define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
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drv2, drv3, pull0, pull1, \
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pull2, pull3) \
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{ \
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.bank_num = id, \
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.nr_pins = pins, \
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.name = label, \
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.iomux = { \
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{ .offset = -1 }, \
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{ .offset = -1 }, \
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{ .offset = -1 }, \
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{ .offset = -1 }, \
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}, \
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.drv = { \
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{ .drv_type = drv0, .offset = -1 }, \
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{ .drv_type = drv1, .offset = -1 }, \
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{ .drv_type = drv2, .offset = -1 }, \
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{ .drv_type = drv3, .offset = -1 }, \
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}, \
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.pull_type[0] = pull0, \
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.pull_type[1] = pull1, \
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.pull_type[2] = pull2, \
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.pull_type[3] = pull3, \
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}
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#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
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iom2, iom3, drv0, drv1, drv2, \
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drv3, offset0, offset1, \
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@ -220,6 +256,34 @@ struct rockchip_pin_bank {
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}, \
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}
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#define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
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label, iom0, iom1, iom2, \
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iom3, drv0, drv1, drv2, \
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drv3, offset0, offset1, \
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offset2, offset3, pull0, \
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pull1, pull2, pull3) \
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{ \
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.bank_num = id, \
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.nr_pins = pins, \
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.name = label, \
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.iomux = { \
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{ .type = iom0, .offset = -1 }, \
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{ .type = iom1, .offset = -1 }, \
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{ .type = iom2, .offset = -1 }, \
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{ .type = iom3, .offset = -1 }, \
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}, \
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.drv = { \
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{ .drv_type = drv0, .offset = offset0 }, \
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{ .drv_type = drv1, .offset = offset1 }, \
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{ .drv_type = drv2, .offset = offset2 }, \
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{ .drv_type = drv3, .offset = offset3 }, \
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}, \
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.pull_type[0] = pull0, \
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.pull_type[1] = pull1, \
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.pull_type[2] = pull2, \
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.pull_type[3] = pull3, \
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}
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/**
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*/
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struct rockchip_pin_ctrl {
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@ -1020,12 +1084,27 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
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return ret;
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}
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static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
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{
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PIN_CONFIG_BIAS_DISABLE,
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PIN_CONFIG_BIAS_PULL_UP,
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PIN_CONFIG_BIAS_PULL_DOWN,
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PIN_CONFIG_BIAS_BUS_HOLD
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},
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{
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PIN_CONFIG_BIAS_DISABLE,
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PIN_CONFIG_BIAS_PULL_DOWN,
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PIN_CONFIG_BIAS_DISABLE,
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PIN_CONFIG_BIAS_PULL_UP
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},
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};
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static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
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{
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struct rockchip_pinctrl *info = bank->drvdata;
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struct rockchip_pin_ctrl *ctrl = info->ctrl;
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struct regmap *regmap;
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int reg, ret;
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int reg, ret, pull_type;
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u8 bit;
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u32 data;
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@ -1048,22 +1127,11 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
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case RK3288:
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case RK3368:
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case RK3399:
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pull_type = bank->pull_type[pin_num / 8];
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data >>= bit;
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data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
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switch (data) {
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case 0:
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return PIN_CONFIG_BIAS_DISABLE;
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case 1:
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return PIN_CONFIG_BIAS_PULL_UP;
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case 2:
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return PIN_CONFIG_BIAS_PULL_DOWN;
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case 3:
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return PIN_CONFIG_BIAS_BUS_HOLD;
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}
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dev_err(info->dev, "unknown pull setting\n");
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return -EIO;
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return rockchip_pull_list[pull_type][data];
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default:
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dev_err(info->dev, "unsupported pinctrl type\n");
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return -EINVAL;
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@ -1076,7 +1144,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
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struct rockchip_pinctrl *info = bank->drvdata;
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struct rockchip_pin_ctrl *ctrl = info->ctrl;
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struct regmap *regmap;
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int reg, ret;
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int reg, ret, i, pull_type;
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unsigned long flags;
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u8 bit;
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u32 data, rmask;
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@ -1105,30 +1173,28 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
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case RK3288:
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case RK3368:
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case RK3399:
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pull_type = bank->pull_type[pin_num / 8];
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ret = -EINVAL;
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for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
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i++) {
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if (rockchip_pull_list[pull_type][i] == pull) {
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ret = i;
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break;
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}
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}
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if (ret < 0) {
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dev_err(info->dev, "unsupported pull setting %d\n",
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pull);
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return ret;
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}
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spin_lock_irqsave(&bank->slock, flags);
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/* enable the write to the equivalent lower bits */
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data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
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rmask = data | (data >> 16);
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switch (pull) {
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case PIN_CONFIG_BIAS_DISABLE:
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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data |= (1 << bit);
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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data |= (2 << bit);
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break;
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case PIN_CONFIG_BIAS_BUS_HOLD:
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data |= (3 << bit);
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break;
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default:
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spin_unlock_irqrestore(&bank->slock, flags);
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dev_err(info->dev, "unsupported pull setting %d\n",
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pull);
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return -EINVAL;
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}
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data |= (ret << bit);
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ret = regmap_update_bits(regmap, reg, rmask, data);
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@ -2552,19 +2618,24 @@ static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
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};
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static struct rockchip_pin_bank rk3399_pin_banks[] = {
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PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(0, 32, "gpio0", IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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DRV_TYPE_IO_1V8_ONLY,
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DRV_TYPE_IO_1V8_ONLY,
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DRV_TYPE_IO_DEFAULT,
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DRV_TYPE_IO_DEFAULT,
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0x0,
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0x8,
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-1,
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-1
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),
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PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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DRV_TYPE_IO_1V8_ONLY,
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DRV_TYPE_IO_1V8_ONLY,
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DRV_TYPE_IO_DEFAULT,
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DRV_TYPE_IO_DEFAULT,
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0x0,
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0x8,
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-1,
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-1,
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PULL_TYPE_IO_1V8_ONLY,
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PULL_TYPE_IO_1V8_ONLY,
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PULL_TYPE_IO_DEFAULT,
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PULL_TYPE_IO_DEFAULT
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),
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PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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@ -2578,11 +2649,15 @@ static struct rockchip_pin_bank rk3399_pin_banks[] = {
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0x30,
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0x38
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),
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PIN_BANK_DRV_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
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DRV_TYPE_IO_1V8_OR_3V0,
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DRV_TYPE_IO_1V8_ONLY,
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DRV_TYPE_IO_1V8_ONLY
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),
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PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
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DRV_TYPE_IO_1V8_OR_3V0,
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DRV_TYPE_IO_1V8_ONLY,
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DRV_TYPE_IO_1V8_ONLY,
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PULL_TYPE_IO_DEFAULT,
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PULL_TYPE_IO_DEFAULT,
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PULL_TYPE_IO_1V8_ONLY,
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PULL_TYPE_IO_1V8_ONLY
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),
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PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
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DRV_TYPE_IO_3V3_ONLY,
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DRV_TYPE_IO_3V3_ONLY,
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