dmaengine: fsl-edma: correct max_segment_size setting
[ Upstream commit a79f949a5ce1d45329d63742c2a995f2b47f9852 ]
Correcting the previous setting of 0x3fff to the actual value of 0x7fff.
Introduced new macro 'EDMA_TCD_ITER_MASK' for improved code clarity and
utilization of FIELD_GET to obtain the accurate maximum value.
Cc: stable@vger.kernel.org
Fixes: e067485394
("dmaengine: fsl-edma: support edma memcpy")
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20240207194733.2112870-1-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -30,8 +30,9 @@
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#define EDMA_TCD_ATTR_SSIZE(x) (((x) & GENMASK(2, 0)) << 8)
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#define EDMA_TCD_ATTR_SMOD(x) (((x) & GENMASK(4, 0)) << 11)
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#define EDMA_TCD_CITER_CITER(x) ((x) & GENMASK(14, 0))
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#define EDMA_TCD_BITER_BITER(x) ((x) & GENMASK(14, 0))
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#define EDMA_TCD_ITER_MASK GENMASK(14, 0)
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#define EDMA_TCD_CITER_CITER(x) ((x) & EDMA_TCD_ITER_MASK)
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#define EDMA_TCD_BITER_BITER(x) ((x) & EDMA_TCD_ITER_MASK)
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#define EDMA_TCD_CSR_START BIT(0)
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#define EDMA_TCD_CSR_INT_MAJOR BIT(1)
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@ -10,6 +10,7 @@
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*/
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#include <dt-bindings/dma/fsl-edma.h>
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#include <linux/bitfield.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/clk.h>
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@ -589,7 +590,8 @@ static int fsl_edma_probe(struct platform_device *pdev)
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DMAENGINE_ALIGN_32_BYTES;
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/* Per worst case 'nbytes = 1' take CITER as the max_seg_size */
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dma_set_max_seg_size(fsl_edma->dma_dev.dev, 0x3fff);
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dma_set_max_seg_size(fsl_edma->dma_dev.dev,
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FIELD_GET(EDMA_TCD_ITER_MASK, EDMA_TCD_ITER_MASK));
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fsl_edma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
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