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Pin control fixes for v5.4: 

- Handle multiple instances of Intel chips without complaining.
 - Restore the Intel Strago DMI workaround
 - Make the Armada 37xx handle pins over 32
 - Fix the polarity of the LED group on Armada 37xx
 - Fix an off-by-one bug in the NS2 driver
 - Fix error path for iproc's platform_get_irq()
 - Fix error path on the STMFX driver
 - Fix a typo in the Berlin AS370 driver
 - Fix up misc errors in the Aspeed 2600 BMC support
 - Fix a stray SPDX tag
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Merge tag 'pinctrl-v5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:
 "Here is a bunch of pin control fixes. I was lagging behind on this
  one, some fixes should have come in earlier, sorry about that.

  Anyways here it is, pretty straight-forward fixes, the Strago fix
  stand out as something serious affecting a lot of machines.

  Summary:
   - Handle multiple instances of Intel chips without complaining.
   - Restore the Intel Strago DMI workaround
   - Make the Armada 37xx handle pins over 32
   - Fix the polarity of the LED group on Armada 37xx
   - Fix an off-by-one bug in the NS2 driver
   - Fix error path for iproc's platform_get_irq()
   - Fix error path on the STMFX driver
   - Fix a typo in the Berlin AS370 driver
   - Fix up misc errors in the Aspeed 2600 BMC support
   - Fix a stray SPDX tag"

* tag 'pinctrl-v5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: aspeed-g6: Rename SD3 to EMMC and rework pin groups
  pinctrl: aspeed-g6: Fix UART13 group pinmux
  pinctrl: aspeed-g6: Make SIG_DESC_CLEAR() behave intuitively
  pinctrl: aspeed-g6: Fix I3C3/I3C4 pinmux configuration
  pinctrl: aspeed-g6: Fix I2C14 SDA description
  pinctrl: aspeed-g6: Sort pins for sanity
  dt-bindings: pinctrl: aspeed-g6: Rework SD3 function and groups
  pinctrl: berlin: as370: fix a typo s/spififib/spdifib
  pinctrl: armada-37xx: swap polarity on LED group
  pinctrl: stmfx: fix null pointer on remove
  pinctrl: iproc: allow for error from platform_get_irq()
  pinctrl: ns2: Fix off by one bugs in ns2_pinmux_enable()
  pinctrl: bcm-iproc: Use SPDX header
  pinctrl: armada-37xx: fix control of pins 32 and up
  pinctrl: cherryview: restore Strago DMI workaround for all versions
  pinctrl: intel: Allocate IRQ chip dynamic
This commit is contained in:
Linus Torvalds 2019-10-22 06:40:07 -04:00
parent 7d194c2100 d6e7a1a511
commit 3b7c59a195
10 changed files with 131 additions and 159 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

86
Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
View File

@ -33,13 +33,13 @@ patternProperties:
allOf: allOf:
- $ref: "/schemas/types.yaml#/definitions/string" - $ref: "/schemas/types.yaml#/definitions/string"
- enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, - enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, ESPI, ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMC,
ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWSPIWP, GPIT0, GPIT1, ESPI, ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWSPIWP, GPIT0,
GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, GPIU2, GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1,
GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, I2C1, I2C10, I2C11, I2C12, GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, I2C1, I2C10, I2C11,
I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, I2C6,
I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ, LPC, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ,
LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2,
MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2, MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2,
NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3,
NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1,
@ -48,47 +48,45 @@ patternProperties:
PWM8, PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, PWM8, PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3,
RMII4, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, RMII4, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12,
SALT13, SALT14, SALT15, SALT16, SALT2, SALT3, SALT4, SALT5, SALT13, SALT14, SALT15, SALT16, SALT2, SALT3, SALT4, SALT5,
SALT6, SALT7, SALT8, SALT9, SD1, SD2, SD3, SD3DAT4, SD3DAT5, SALT6, SALT7, SALT8, SALT9, SD1, SD2, SGPM1, SGPS1, SIOONCTRL,
SD3DAT6, SD3DAT7, SGPM1, SGPS1, SIOONCTRL, SIOPBI, SIOPBO, SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1,
SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1,
SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3,
TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2,
TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12, UART13,
TXD2, TXD3, TXD4, UART10, UART11, UART12, UART13, UART6, UART7, UART6, UART7, UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2,
UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST3, WDTRST4, ]
WDTRST4, ]
groups: groups:
allOf: allOf:
- $ref: "/schemas/types.yaml#/definitions/string" - $ref: "/schemas/types.yaml#/definitions/string"
- enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, - enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, ESPI, ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMCG1,
ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWQSPID, FWSPIWP, GPIT0, EMMCG4, EMMCG8, ESPI, ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID,
GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, FWQSPID, FWSPIWP, GPIT0, GPIT1, GPIT2, GPIT3, GPIT4, GPIT5,
GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, HVI3C3, HVI3C4, I2C1, GPIT6, GPIT7, GPIU0, GPIU1, GPIU2, GPIU3, GPIU4, GPIU5, GPIU6,
I2C10, I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, GPIU7, HVI3C3, HVI3C4, I2C1, I2C10, I2C11, I2C12, I2C13, I2C14,
I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9,
JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD,
MACLINK1, MACLINK2, MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, MACLINK3, MACLINK4,
MDIO4, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1,
NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2,
NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4,
PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1, PWM12G0, PWM12G1, OSCCLK, PEWAKE, PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1,
PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0, PWM15G1, PWM2, PWM3, PWM12G0, PWM12G1, PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0,
PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1, PWM9G0, PWM9G1, QSPI1, PWM15G1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1,
QSPI2, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, PWM9G0, PWM9G1, QSPI1, QSPI2, RGMII1, RGMII2, RGMII3, RGMII4,
RMII4, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10G0, SALT10G1, RMII1, RMII2, RMII3, RMII4, RXD1, RXD2, RXD3, RXD4, SALT1,
SALT11G0, SALT11G1, SALT12G0, SALT12G1, SALT13G0, SALT13G1, SALT10G0, SALT10G1, SALT11G0, SALT11G1, SALT12G0, SALT12G1,
SALT14G0, SALT14G1, SALT15G0, SALT15G1, SALT16G0, SALT16G1, SALT13G0, SALT13G1, SALT14G0, SALT14G1, SALT15G0, SALT15G1,
SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, SALT9G0, SALT16G0, SALT16G1, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7,
SALT9G1, SD1, SD2, SD3, SD3DAT4, SD3DAT5, SD3DAT6, SD3DAT7, SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPS1, SIOONCTRL,
SGPM1, SGPS1, SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1,
SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1,
SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13, TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3,
TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8, TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2,
TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4, THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12G0,
UART10, UART11, UART12G0, UART12G1, UART13G0, UART13G1, UART6, UART12G1, UART13G0, UART13G1, UART6, UART7, UART8, UART9, VB,
UART7, UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4, ]
WDTRST4, ]
required: required:
- compatible - compatible

124
drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
View File

@ -87,7 +87,7 @@ FUNC_GROUP_DECL(MACLINK3, L23);
#define K25 7 #define K25 7
SIG_EXPR_LIST_DECL_SESG(K25, MACLINK4, MACLINK4, SIG_DESC_SET(SCU410, 7)); SIG_EXPR_LIST_DECL_SESG(K25, MACLINK4, MACLINK4, SIG_DESC_SET(SCU410, 7));
SIG_EXPR_LIST_DECL_SESG(K25, SDA14, SDA14, SIG_DESC_SET(SCU4B0, 7)); SIG_EXPR_LIST_DECL_SESG(K25, SDA14, I2C14, SIG_DESC_SET(SCU4B0, 7));
PIN_DECL_2(K25, GPIOA7, MACLINK4, SDA14); PIN_DECL_2(K25, GPIOA7, MACLINK4, SDA14);
FUNC_GROUP_DECL(MACLINK4, K25); FUNC_GROUP_DECL(MACLINK4, K25);
@ -1262,13 +1262,13 @@ GROUP_DECL(SPI1, AB11, AC11, AA11);
#define AD11 206 #define AD11 206
SIG_EXPR_LIST_DECL_SEMG(AD11, SPI1DQ2, QSPI1, SPI1, SIG_DESC_SET(SCU438, 14)); SIG_EXPR_LIST_DECL_SEMG(AD11, SPI1DQ2, QSPI1, SPI1, SIG_DESC_SET(SCU438, 14));
SIG_EXPR_LIST_DECL_SEMG(AD11, TXD13, UART13G1, UART13, SIG_EXPR_LIST_DECL_SEMG(AD11, TXD13, UART13G1, UART13,
SIG_DESC_SET(SCU438, 14)); SIG_DESC_CLEAR(SCU4B8, 2), SIG_DESC_SET(SCU4D8, 14));
PIN_DECL_2(AD11, GPIOZ6, SPI1DQ2, TXD13); PIN_DECL_2(AD11, GPIOZ6, SPI1DQ2, TXD13);
#define AF10 207 #define AF10 207
SIG_EXPR_LIST_DECL_SEMG(AF10, SPI1DQ3, QSPI1, SPI1, SIG_DESC_SET(SCU438, 15)); SIG_EXPR_LIST_DECL_SEMG(AF10, SPI1DQ3, QSPI1, SPI1, SIG_DESC_SET(SCU438, 15));
SIG_EXPR_LIST_DECL_SEMG(AF10, RXD13, UART13G1, UART13, SIG_EXPR_LIST_DECL_SEMG(AF10, RXD13, UART13G1, UART13,
SIG_DESC_SET(SCU438, 15)); SIG_DESC_CLEAR(SCU4B8, 3), SIG_DESC_SET(SCU4D8, 15));
PIN_DECL_2(AF10, GPIOZ7, SPI1DQ3, RXD13); PIN_DECL_2(AF10, GPIOZ7, SPI1DQ3, RXD13);
GROUP_DECL(QSPI1, AB11, AC11, AA11, AD11, AF10); GROUP_DECL(QSPI1, AB11, AC11, AA11, AD11, AF10);
@ -1440,91 +1440,85 @@ FUNC_GROUP_DECL(RGMII2, D4, C2, C1, D3, E4, F5, D2, E3, D1, F4, E2, E1);
FUNC_GROUP_DECL(RMII2, D4, C2, C1, D3, D2, D1, F4, E2, E1); FUNC_GROUP_DECL(RMII2, D4, C2, C1, D3, D2, D1, F4, E2, E1);
#define AB4 232 #define AB4 232
SIG_EXPR_LIST_DECL_SESG(AB4, SD3CLK, SD3, SIG_DESC_SET(SCU400, 24)); SIG_EXPR_LIST_DECL_SEMG(AB4, EMMCCLK, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 24));
PIN_DECL_1(AB4, GPIO18D0, SD3CLK); PIN_DECL_1(AB4, GPIO18D0, EMMCCLK);
#define AA4 233 #define AA4 233
SIG_EXPR_LIST_DECL_SESG(AA4, SD3CMD, SD3, SIG_DESC_SET(SCU400, 25)); SIG_EXPR_LIST_DECL_SEMG(AA4, EMMCCMD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 25));
PIN_DECL_1(AA4, GPIO18D1, SD3CMD); PIN_DECL_1(AA4, GPIO18D1, EMMCCMD);
#define AC4 234 #define AC4 234
SIG_EXPR_LIST_DECL_SESG(AC4, SD3DAT0, SD3, SIG_DESC_SET(SCU400, 26)); SIG_EXPR_LIST_DECL_SEMG(AC4, EMMCDAT0, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 26));
PIN_DECL_1(AC4, GPIO18D2, SD3DAT0); PIN_DECL_1(AC4, GPIO18D2, EMMCDAT0);
#define AA5 235 #define AA5 235
SIG_EXPR_LIST_DECL_SESG(AA5, SD3DAT1, SD3, SIG_DESC_SET(SCU400, 27)); SIG_EXPR_LIST_DECL_SEMG(AA5, EMMCDAT1, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 27));
PIN_DECL_1(AA5, GPIO18D3, SD3DAT1); PIN_DECL_1(AA5, GPIO18D3, EMMCDAT1);
#define Y5 236 #define Y5 236
SIG_EXPR_LIST_DECL_SESG(Y5, SD3DAT2, SD3, SIG_DESC_SET(SCU400, 28)); SIG_EXPR_LIST_DECL_SEMG(Y5, EMMCDAT2, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 28));
PIN_DECL_1(Y5, GPIO18D4, SD3DAT2); PIN_DECL_1(Y5, GPIO18D4, EMMCDAT2);
#define AB5 237 #define AB5 237
SIG_EXPR_LIST_DECL_SESG(AB5, SD3DAT3, SD3, SIG_DESC_SET(SCU400, 29)); SIG_EXPR_LIST_DECL_SEMG(AB5, EMMCDAT3, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 29));
PIN_DECL_1(AB5, GPIO18D5, SD3DAT3); PIN_DECL_1(AB5, GPIO18D5, EMMCDAT3);
#define AB6 238 #define AB6 238
SIG_EXPR_LIST_DECL_SESG(AB6, SD3CD, SD3, SIG_DESC_SET(SCU400, 30)); SIG_EXPR_LIST_DECL_SEMG(AB6, EMMCCD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 30));
PIN_DECL_1(AB6, GPIO18D6, SD3CD); PIN_DECL_1(AB6, GPIO18D6, EMMCCD);
#define AC5 239 #define AC5 239
SIG_EXPR_LIST_DECL_SESG(AC5, SD3WP, SD3, SIG_DESC_SET(SCU400, 31)); SIG_EXPR_LIST_DECL_SEMG(AC5, EMMCWP, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 31));
PIN_DECL_1(AC5, GPIO18D7, SD3WP); PIN_DECL_1(AC5, GPIO18D7, EMMCWP);
FUNC_GROUP_DECL(SD3, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5); GROUP_DECL(EMMCG1, AB4, AA4, AC4, AB6, AC5);
GROUP_DECL(EMMCG4, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5);
#define Y1 240 #define Y1 240
SIG_EXPR_LIST_DECL_SEMG(Y1, FWSPIDCS, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3)); SIG_EXPR_LIST_DECL_SEMG(Y1, FWSPIDCS, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3));
SIG_EXPR_LIST_DECL_SESG(Y1, VBCS, VB, SIG_DESC_SET(SCU500, 5)); SIG_EXPR_LIST_DECL_SESG(Y1, VBCS, VB, SIG_DESC_SET(SCU500, 5));
SIG_EXPR_LIST_DECL_SESG(Y1, SD3DAT4, SD3DAT4, SIG_DESC_SET(SCU404, 0)); SIG_EXPR_LIST_DECL_SEMG(Y1, EMMCDAT4, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 0));
PIN_DECL_3(Y1, GPIO18E0, FWSPIDCS, VBCS, SD3DAT4); PIN_DECL_3(Y1, GPIO18E0, FWSPIDCS, VBCS, EMMCDAT4);
FUNC_GROUP_DECL(SD3DAT4, Y1);
#define Y2 241 #define Y2 241
SIG_EXPR_LIST_DECL_SEMG(Y2, FWSPIDCK, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3)); SIG_EXPR_LIST_DECL_SEMG(Y2, FWSPIDCK, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3));
SIG_EXPR_LIST_DECL_SESG(Y2, VBCK, VB, SIG_DESC_SET(SCU500, 5)); SIG_EXPR_LIST_DECL_SESG(Y2, VBCK, VB, SIG_DESC_SET(SCU500, 5));
SIG_EXPR_LIST_DECL_SESG(Y2, SD3DAT5, SD3DAT5, SIG_DESC_SET(SCU404, 1)); SIG_EXPR_LIST_DECL_SEMG(Y2, EMMCDAT5, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 1));
PIN_DECL_3(Y2, GPIO18E1, FWSPIDCK, VBCK, SD3DAT5); PIN_DECL_3(Y2, GPIO18E1, FWSPIDCK, VBCK, EMMCDAT5);
FUNC_GROUP_DECL(SD3DAT5, Y2);
#define Y3 242 #define Y3 242
SIG_EXPR_LIST_DECL_SEMG(Y3, FWSPIDMOSI, FWSPID, FWSPID, SIG_EXPR_LIST_DECL_SEMG(Y3, FWSPIDMOSI, FWSPID, FWSPID,
SIG_DESC_SET(SCU500, 3)); SIG_DESC_SET(SCU500, 3));
SIG_EXPR_LIST_DECL_SESG(Y3, VBMOSI, VB, SIG_DESC_SET(SCU500, 5)); SIG_EXPR_LIST_DECL_SESG(Y3, VBMOSI, VB, SIG_DESC_SET(SCU500, 5));
SIG_EXPR_LIST_DECL_SESG(Y3, SD3DAT6, SD3DAT6, SIG_DESC_SET(SCU404, 2)); SIG_EXPR_LIST_DECL_SEMG(Y3, EMMCDAT6, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 2));
PIN_DECL_3(Y3, GPIO18E2, FWSPIDMOSI, VBMOSI, SD3DAT6); PIN_DECL_3(Y3, GPIO18E2, FWSPIDMOSI, VBMOSI, EMMCDAT6);
FUNC_GROUP_DECL(SD3DAT6, Y3);
#define Y4 243 #define Y4 243
SIG_EXPR_LIST_DECL_SEMG(Y4, FWSPIDMISO, FWSPID, FWSPID, SIG_EXPR_LIST_DECL_SEMG(Y4, FWSPIDMISO, FWSPID, FWSPID,
SIG_DESC_SET(SCU500, 3)); SIG_DESC_SET(SCU500, 3));
SIG_EXPR_LIST_DECL_SESG(Y4, VBMISO, VB, SIG_DESC_SET(SCU500, 5)); SIG_EXPR_LIST_DECL_SESG(Y4, VBMISO, VB, SIG_DESC_SET(SCU500, 5));
SIG_EXPR_LIST_DECL_SESG(Y4, SD3DAT7, SD3DAT7, SIG_DESC_SET(SCU404, 3)); SIG_EXPR_LIST_DECL_SEMG(Y4, EMMCDAT7, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 3));
PIN_DECL_3(Y4, GPIO18E3, FWSPIDMISO, VBMISO, SD3DAT7); PIN_DECL_3(Y4, GPIO18E3, FWSPIDMISO, VBMISO, EMMCDAT7);
FUNC_GROUP_DECL(SD3DAT7, Y4);
GROUP_DECL(FWSPID, Y1, Y2, Y3, Y4); GROUP_DECL(FWSPID, Y1, Y2, Y3, Y4);
GROUP_DECL(FWQSPID, Y1, Y2, Y3, Y4, AE12, AF12); GROUP_DECL(FWQSPID, Y1, Y2, Y3, Y4, AE12, AF12);
GROUP_DECL(EMMCG8, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5, Y1, Y2, Y3, Y4);
FUNC_DECL_2(FWSPID, FWSPID, FWQSPID); FUNC_DECL_2(FWSPID, FWSPID, FWQSPID);
FUNC_GROUP_DECL(VB, Y1, Y2, Y3, Y4); FUNC_GROUP_DECL(VB, Y1, Y2, Y3, Y4);
FUNC_DECL_3(EMMC, EMMCG1, EMMCG4, EMMCG8);
/* /*
* FIXME: Confirm bits and priorities are the right way around for the * FIXME: Confirm bits and priorities are the right way around for the
* following 4 pins * following 4 pins
*/ */
#define AF25 244 #define AF25 244
SIG_EXPR_LIST_DECL_SEMG(AF25, I3C3SCL, I3C3, I3C3, SIG_DESC_SET(SCU438, 20), SIG_EXPR_LIST_DECL_SEMG(AF25, I3C3SCL, I3C3, I3C3, SIG_DESC_SET(SCU438, 20));
SIG_DESC_SET(SCU4D8, 20)); SIG_EXPR_LIST_DECL_SESG(AF25, FSI1CLK, FSI1, SIG_DESC_SET(SCU4D8, 20));
SIG_EXPR_LIST_DECL_SESG(AF25, FSI1CLK, FSI1, SIG_DESC_CLEAR(SCU438, 20),
SIG_DESC_SET(SCU4D8, 20));
PIN_DECL_(AF25, SIG_EXPR_LIST_PTR(AF25, I3C3SCL), PIN_DECL_(AF25, SIG_EXPR_LIST_PTR(AF25, I3C3SCL),
SIG_EXPR_LIST_PTR(AF25, FSI1CLK)); SIG_EXPR_LIST_PTR(AF25, FSI1CLK));
#define AE26 245 #define AE26 245
SIG_EXPR_LIST_DECL_SEMG(AE26, I3C3SDA, I3C3, I3C3, SIG_DESC_SET(SCU438, 21), SIG_EXPR_LIST_DECL_SEMG(AE26, I3C3SDA, I3C3, I3C3, SIG_DESC_SET(SCU438, 21));
SIG_DESC_SET(SCU4D8, 21)); SIG_EXPR_LIST_DECL_SESG(AE26, FSI1DATA, FSI1, SIG_DESC_SET(SCU4D8, 21));
SIG_EXPR_LIST_DECL_SESG(AE26, FSI1DATA, FSI1, SIG_DESC_CLEAR(SCU438, 21),
SIG_DESC_SET(SCU4D8, 21));
PIN_DECL_(AE26, SIG_EXPR_LIST_PTR(AE26, I3C3SDA), PIN_DECL_(AE26, SIG_EXPR_LIST_PTR(AE26, I3C3SDA),
SIG_EXPR_LIST_PTR(AE26, FSI1DATA)); SIG_EXPR_LIST_PTR(AE26, FSI1DATA));
@ -1533,18 +1527,14 @@ FUNC_DECL_2(I3C3, HVI3C3, I3C3);
FUNC_GROUP_DECL(FSI1, AF25, AE26); FUNC_GROUP_DECL(FSI1, AF25, AE26);
#define AE25 246 #define AE25 246
SIG_EXPR_LIST_DECL_SEMG(AE25, I3C4SCL, I3C4, I3C4, SIG_DESC_SET(SCU438, 22), SIG_EXPR_LIST_DECL_SEMG(AE25, I3C4SCL, I3C4, I3C4, SIG_DESC_SET(SCU438, 22));
SIG_DESC_SET(SCU4D8, 22)); SIG_EXPR_LIST_DECL_SESG(AE25, FSI2CLK, FSI2, SIG_DESC_SET(SCU4D8, 22));
SIG_EXPR_LIST_DECL_SESG(AE25, FSI2CLK, FSI2, SIG_DESC_CLEAR(SCU438, 22),
SIG_DESC_SET(SCU4D8, 22));
PIN_DECL_(AE25, SIG_EXPR_LIST_PTR(AE25, I3C4SCL), PIN_DECL_(AE25, SIG_EXPR_LIST_PTR(AE25, I3C4SCL),
SIG_EXPR_LIST_PTR(AE25, FSI2CLK)); SIG_EXPR_LIST_PTR(AE25, FSI2CLK));
#define AF24 247 #define AF24 247
SIG_EXPR_LIST_DECL_SEMG(AF24, I3C4SDA, I3C4, I3C4, SIG_DESC_SET(SCU438, 23), SIG_EXPR_LIST_DECL_SEMG(AF24, I3C4SDA, I3C4, I3C4, SIG_DESC_SET(SCU438, 23));
SIG_DESC_SET(SCU4D8, 23)); SIG_EXPR_LIST_DECL_SESG(AF24, FSI2DATA, FSI2, SIG_DESC_SET(SCU4D8, 23));
SIG_EXPR_LIST_DECL_SESG(AF24, FSI2DATA, FSI2, SIG_DESC_CLEAR(SCU438, 23),
SIG_DESC_SET(SCU4D8, 23));
PIN_DECL_(AF24, SIG_EXPR_LIST_PTR(AF24, I3C4SDA), PIN_DECL_(AF24, SIG_EXPR_LIST_PTR(AF24, I3C4SDA),
SIG_EXPR_LIST_PTR(AF24, FSI2DATA)); SIG_EXPR_LIST_PTR(AF24, FSI2DATA));
@ -1574,6 +1564,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = {
ASPEED_PINCTRL_PIN(A3), ASPEED_PINCTRL_PIN(A3),
ASPEED_PINCTRL_PIN(AA11), ASPEED_PINCTRL_PIN(AA11),
ASPEED_PINCTRL_PIN(AA12), ASPEED_PINCTRL_PIN(AA12),
ASPEED_PINCTRL_PIN(AA16),
ASPEED_PINCTRL_PIN(AA17),
ASPEED_PINCTRL_PIN(AA23), ASPEED_PINCTRL_PIN(AA23),
ASPEED_PINCTRL_PIN(AA24), ASPEED_PINCTRL_PIN(AA24),
ASPEED_PINCTRL_PIN(AA25), ASPEED_PINCTRL_PIN(AA25),
@ -1585,6 +1577,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = {
ASPEED_PINCTRL_PIN(AB11), ASPEED_PINCTRL_PIN(AB11),
ASPEED_PINCTRL_PIN(AB12), ASPEED_PINCTRL_PIN(AB12),
ASPEED_PINCTRL_PIN(AB15), ASPEED_PINCTRL_PIN(AB15),
ASPEED_PINCTRL_PIN(AB16),
ASPEED_PINCTRL_PIN(AB17),
ASPEED_PINCTRL_PIN(AB18), ASPEED_PINCTRL_PIN(AB18),
ASPEED_PINCTRL_PIN(AB19), ASPEED_PINCTRL_PIN(AB19),
ASPEED_PINCTRL_PIN(AB22), ASPEED_PINCTRL_PIN(AB22),
@ -1602,6 +1596,7 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = {
ASPEED_PINCTRL_PIN(AC11), ASPEED_PINCTRL_PIN(AC11),
ASPEED_PINCTRL_PIN(AC12), ASPEED_PINCTRL_PIN(AC12),
ASPEED_PINCTRL_PIN(AC15), ASPEED_PINCTRL_PIN(AC15),
ASPEED_PINCTRL_PIN(AC16),
ASPEED_PINCTRL_PIN(AC17), ASPEED_PINCTRL_PIN(AC17),
ASPEED_PINCTRL_PIN(AC18), ASPEED_PINCTRL_PIN(AC18),
ASPEED_PINCTRL_PIN(AC19), ASPEED_PINCTRL_PIN(AC19),
@ -1619,6 +1614,7 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = {
ASPEED_PINCTRL_PIN(AD12), ASPEED_PINCTRL_PIN(AD12),
ASPEED_PINCTRL_PIN(AD14), ASPEED_PINCTRL_PIN(AD14),
ASPEED_PINCTRL_PIN(AD15), ASPEED_PINCTRL_PIN(AD15),
ASPEED_PINCTRL_PIN(AD16),
ASPEED_PINCTRL_PIN(AD19), ASPEED_PINCTRL_PIN(AD19),
ASPEED_PINCTRL_PIN(AD20), ASPEED_PINCTRL_PIN(AD20),
ASPEED_PINCTRL_PIN(AD22), ASPEED_PINCTRL_PIN(AD22),
@ -1634,8 +1630,11 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = {
ASPEED_PINCTRL_PIN(AE12), ASPEED_PINCTRL_PIN(AE12),
ASPEED_PINCTRL_PIN(AE14), ASPEED_PINCTRL_PIN(AE14),
ASPEED_PINCTRL_PIN(AE15), ASPEED_PINCTRL_PIN(AE15),
ASPEED_PINCTRL_PIN(AE16),
ASPEED_PINCTRL_PIN(AE18), ASPEED_PINCTRL_PIN(AE18),
ASPEED_PINCTRL_PIN(AE19), ASPEED_PINCTRL_PIN(AE19),
ASPEED_PINCTRL_PIN(AE25),
ASPEED_PINCTRL_PIN(AE26),
ASPEED_PINCTRL_PIN(AE7), ASPEED_PINCTRL_PIN(AE7),
ASPEED_PINCTRL_PIN(AE8), ASPEED_PINCTRL_PIN(AE8),
ASPEED_PINCTRL_PIN(AF10), ASPEED_PINCTRL_PIN(AF10),
@ -1643,6 +1642,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = {
ASPEED_PINCTRL_PIN(AF12), ASPEED_PINCTRL_PIN(AF12),
ASPEED_PINCTRL_PIN(AF14), ASPEED_PINCTRL_PIN(AF14),
ASPEED_PINCTRL_PIN(AF15), ASPEED_PINCTRL_PIN(AF15),
ASPEED_PINCTRL_PIN(AF24),
ASPEED_PINCTRL_PIN(AF25),
ASPEED_PINCTRL_PIN(AF7), ASPEED_PINCTRL_PIN(AF7),
ASPEED_PINCTRL_PIN(AF8), ASPEED_PINCTRL_PIN(AF8),
ASPEED_PINCTRL_PIN(AF9), ASPEED_PINCTRL_PIN(AF9),
@ -1792,17 +1793,6 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = {
ASPEED_PINCTRL_PIN(Y3), ASPEED_PINCTRL_PIN(Y3),
ASPEED_PINCTRL_PIN(Y4), ASPEED_PINCTRL_PIN(Y4),
ASPEED_PINCTRL_PIN(Y5), ASPEED_PINCTRL_PIN(Y5),
ASPEED_PINCTRL_PIN(AB16),
ASPEED_PINCTRL_PIN(AA17),
ASPEED_PINCTRL_PIN(AB17),
ASPEED_PINCTRL_PIN(AE16),
ASPEED_PINCTRL_PIN(AC16),
ASPEED_PINCTRL_PIN(AA16),
ASPEED_PINCTRL_PIN(AD16),
ASPEED_PINCTRL_PIN(AF25),
ASPEED_PINCTRL_PIN(AE26),
ASPEED_PINCTRL_PIN(AE25),
ASPEED_PINCTRL_PIN(AF24),
}; };
static const struct aspeed_pin_group aspeed_g6_groups[] = { static const struct aspeed_pin_group aspeed_g6_groups[] = {
@ -1976,11 +1966,9 @@ static const struct aspeed_pin_group aspeed_g6_groups[] = {
ASPEED_PINCTRL_GROUP(SALT9G1), ASPEED_PINCTRL_GROUP(SALT9G1),
ASPEED_PINCTRL_GROUP(SD1), ASPEED_PINCTRL_GROUP(SD1),
ASPEED_PINCTRL_GROUP(SD2), ASPEED_PINCTRL_GROUP(SD2),
ASPEED_PINCTRL_GROUP(SD3), ASPEED_PINCTRL_GROUP(EMMCG1),
ASPEED_PINCTRL_GROUP(SD3DAT4), ASPEED_PINCTRL_GROUP(EMMCG4),
ASPEED_PINCTRL_GROUP(SD3DAT5), ASPEED_PINCTRL_GROUP(EMMCG8),
ASPEED_PINCTRL_GROUP(SD3DAT6),
ASPEED_PINCTRL_GROUP(SD3DAT7),
ASPEED_PINCTRL_GROUP(SGPM1), ASPEED_PINCTRL_GROUP(SGPM1),
ASPEED_PINCTRL_GROUP(SGPS1), ASPEED_PINCTRL_GROUP(SGPS1),
ASPEED_PINCTRL_GROUP(SIOONCTRL), ASPEED_PINCTRL_GROUP(SIOONCTRL),
@ -2059,6 +2047,7 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = {
ASPEED_PINCTRL_FUNC(ADC8), ASPEED_PINCTRL_FUNC(ADC8),
ASPEED_PINCTRL_FUNC(ADC9), ASPEED_PINCTRL_FUNC(ADC9),
ASPEED_PINCTRL_FUNC(BMCINT), ASPEED_PINCTRL_FUNC(BMCINT),
ASPEED_PINCTRL_FUNC(EMMC),
ASPEED_PINCTRL_FUNC(ESPI), ASPEED_PINCTRL_FUNC(ESPI),
ASPEED_PINCTRL_FUNC(ESPIALT), ASPEED_PINCTRL_FUNC(ESPIALT),
ASPEED_PINCTRL_FUNC(FSI1), ASPEED_PINCTRL_FUNC(FSI1),
@ -2191,11 +2180,6 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = {
ASPEED_PINCTRL_FUNC(SALT9), ASPEED_PINCTRL_FUNC(SALT9),
ASPEED_PINCTRL_FUNC(SD1), ASPEED_PINCTRL_FUNC(SD1),
ASPEED_PINCTRL_FUNC(SD2), ASPEED_PINCTRL_FUNC(SD2),
ASPEED_PINCTRL_FUNC(SD3),
ASPEED_PINCTRL_FUNC(SD3DAT4),
ASPEED_PINCTRL_FUNC(SD3DAT5),
ASPEED_PINCTRL_FUNC(SD3DAT6),
ASPEED_PINCTRL_FUNC(SD3DAT7),
ASPEED_PINCTRL_FUNC(SGPM1), ASPEED_PINCTRL_FUNC(SGPM1),
ASPEED_PINCTRL_FUNC(SGPS1), ASPEED_PINCTRL_FUNC(SGPS1),
ASPEED_PINCTRL_FUNC(SIOONCTRL), ASPEED_PINCTRL_FUNC(SIOONCTRL),

3
drivers/pinctrl/aspeed/pinmux-aspeed.h
View File

@ -508,7 +508,7 @@ struct aspeed_pin_desc {
* @idx: The bit index in the register * @idx: The bit index in the register
*/ */
#define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1) #define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1)
#define SIG_DESC_CLEAR(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 0) #define SIG_DESC_CLEAR(reg, idx) { ASPEED_IP_SCU, reg, BIT_MASK(idx), 0, 0 }
#define SIG_DESC_LIST_SYM(sig, group) sig_descs_ ## sig ## _ ## group #define SIG_DESC_LIST_SYM(sig, group) sig_descs_ ## sig ## _ ## group
#define SIG_DESC_LIST_DECL(sig, group, ...) \ #define SIG_DESC_LIST_DECL(sig, group, ...) \
@ -738,6 +738,7 @@ struct aspeed_pin_desc {
static const char *FUNC_SYM(func)[] = { __VA_ARGS__ } static const char *FUNC_SYM(func)[] = { __VA_ARGS__ }
#define FUNC_DECL_2(func, one, two) FUNC_DECL_(func, #one, #two) #define FUNC_DECL_2(func, one, two) FUNC_DECL_(func, #one, #two)
#define FUNC_DECL_3(func, one, two, three) FUNC_DECL_(func, #one, #two, #three)
#define FUNC_GROUP_DECL(func, ...) \ #define FUNC_GROUP_DECL(func, ...) \
GROUP_DECL(func, __VA_ARGS__); \ GROUP_DECL(func, __VA_ARGS__); \

12
drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
View File

@ -1,14 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/* /*
* Copyright (C) 2014-2017 Broadcom * Copyright (C) 2014-2017 Broadcom
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/ */
/* /*
@ -853,7 +845,7 @@ static int iproc_gpio_probe(struct platform_device *pdev)
/* optional GPIO interrupt support */ /* optional GPIO interrupt support */
irq = platform_get_irq(pdev, 0); irq = platform_get_irq(pdev, 0);
if (irq) { if (irq > 0) {
struct irq_chip *irqc; struct irq_chip *irqc;
struct gpio_irq_chip *girq; struct gpio_irq_chip *girq;

4
drivers/pinctrl/bcm/pinctrl-ns2-mux.c
View File

@ -640,8 +640,8 @@ static int ns2_pinmux_enable(struct pinctrl_dev *pctrl_dev,
const struct ns2_pin_function *func; const struct ns2_pin_function *func;
const struct ns2_pin_group *grp; const struct ns2_pin_group *grp;
if (grp_select > pinctrl->num_groups || if (grp_select >= pinctrl->num_groups ||
func_select > pinctrl->num_functions) func_select >= pinctrl->num_functions)
return -EINVAL; return -EINVAL;
func = &pinctrl->functions[func_select]; func = &pinctrl->functions[func_select];

2
drivers/pinctrl/berlin/pinctrl-as370.c
View File

@ -43,7 +43,7 @@ static const struct berlin_desc_group as370_soc_pinctrl_groups[] = {
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO5 */ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO5 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* DO3 */ BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* DO3 */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), /* PWM5 */ BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), /* PWM5 */
BERLIN_PINCTRL_FUNCTION(0x3, "spififib"), /* SPDIFIB */ BERLIN_PINCTRL_FUNCTION(0x3, "spdifib"), /* SPDIFIB */
BERLIN_PINCTRL_FUNCTION(0x4, "spdifo"), /* SPDIFO */ BERLIN_PINCTRL_FUNCTION(0x4, "spdifo"), /* SPDIFO */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG5 */ BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG5 */
BERLIN_PINCTRL_GROUP("I2S1_MCLK", 0x0, 0x3, 0x12, BERLIN_PINCTRL_GROUP("I2S1_MCLK", 0x0, 0x3, 0x12,

4
drivers/pinctrl/intel/pinctrl-cherryview.c
View File

@ -1513,7 +1513,6 @@ static const struct dmi_system_id chv_no_valid_mask[] = {
.matches = { .matches = {
DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"), DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"),
DMI_MATCH(DMI_PRODUCT_VERSION, "1.0"),
}, },
}, },
{ {
@ -1521,7 +1520,6 @@ static const struct dmi_system_id chv_no_valid_mask[] = {
.matches = { .matches = {
DMI_MATCH(DMI_SYS_VENDOR, "HP"), DMI_MATCH(DMI_SYS_VENDOR, "HP"),
DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"), DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
DMI_MATCH(DMI_PRODUCT_VERSION, "1.0"),
}, },
}, },
{ {
@ -1529,7 +1527,6 @@ static const struct dmi_system_id chv_no_valid_mask[] = {
.matches = { .matches = {
DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"), DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"),
DMI_MATCH(DMI_PRODUCT_VERSION, "1.0"),
}, },
}, },
{ {
@ -1537,7 +1534,6 @@ static const struct dmi_system_id chv_no_valid_mask[] = {
.matches = { .matches = {
DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
DMI_MATCH(DMI_PRODUCT_NAME, "Celes"), DMI_MATCH(DMI_PRODUCT_NAME, "Celes"),
DMI_MATCH(DMI_PRODUCT_VERSION, "1.0"),
}, },
}, },
{} {}

27
drivers/pinctrl/intel/pinctrl-intel.c
View File

@ -96,6 +96,7 @@ struct intel_pinctrl_context {
* @pctldesc: Pin controller description * @pctldesc: Pin controller description
* @pctldev: Pointer to the pin controller device * @pctldev: Pointer to the pin controller device
* @chip: GPIO chip in this pin controller * @chip: GPIO chip in this pin controller
* @irqchip: IRQ chip in this pin controller
* @soc: SoC/PCH specific pin configuration data * @soc: SoC/PCH specific pin configuration data
* @communities: All communities in this pin controller * @communities: All communities in this pin controller
* @ncommunities: Number of communities in this pin controller * @ncommunities: Number of communities in this pin controller
@ -108,6 +109,7 @@ struct intel_pinctrl {
struct pinctrl_desc pctldesc; struct pinctrl_desc pctldesc;
struct pinctrl_dev *pctldev; struct pinctrl_dev *pctldev;
struct gpio_chip chip; struct gpio_chip chip;
struct irq_chip irqchip;
const struct intel_pinctrl_soc_data *soc; const struct intel_pinctrl_soc_data *soc;
struct intel_community *communities; struct intel_community *communities;
size_t ncommunities; size_t ncommunities;
@ -1139,16 +1141,6 @@ static irqreturn_t intel_gpio_irq(int irq, void *data)
return ret; return ret;
} }
static struct irq_chip intel_gpio_irqchip = {
.name = "intel-gpio",
.irq_ack = intel_gpio_irq_ack,
.irq_mask = intel_gpio_irq_mask,
.irq_unmask = intel_gpio_irq_unmask,
.irq_set_type = intel_gpio_irq_type,
.irq_set_wake = intel_gpio_irq_wake,
.flags = IRQCHIP_MASK_ON_SUSPEND,
};
static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl, static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl,
const struct intel_community *community) const struct intel_community *community)
{ {
@ -1198,12 +1190,22 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
pctrl->chip = intel_gpio_chip; pctrl->chip = intel_gpio_chip;
/* Setup GPIO chip */
pctrl->chip.ngpio = intel_gpio_ngpio(pctrl); pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
pctrl->chip.label = dev_name(pctrl->dev); pctrl->chip.label = dev_name(pctrl->dev);
pctrl->chip.parent = pctrl->dev; pctrl->chip.parent = pctrl->dev;
pctrl->chip.base = -1; pctrl->chip.base = -1;
pctrl->irq = irq; pctrl->irq = irq;
/* Setup IRQ chip */
pctrl->irqchip.name = dev_name(pctrl->dev);
pctrl->irqchip.irq_ack = intel_gpio_irq_ack;
pctrl->irqchip.irq_mask = intel_gpio_irq_mask;
pctrl->irqchip.irq_unmask = intel_gpio_irq_unmask;
pctrl->irqchip.irq_set_type = intel_gpio_irq_type;
pctrl->irqchip.irq_set_wake = intel_gpio_irq_wake;
pctrl->irqchip.flags = IRQCHIP_MASK_ON_SUSPEND;
ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
if (ret) { if (ret) {
dev_err(pctrl->dev, "failed to register gpiochip\n"); dev_err(pctrl->dev, "failed to register gpiochip\n");
@ -1233,15 +1235,14 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
return ret; return ret;
} }
ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0, ret = gpiochip_irqchip_add(&pctrl->chip, &pctrl->irqchip, 0,
handle_bad_irq, IRQ_TYPE_NONE); handle_bad_irq, IRQ_TYPE_NONE);
if (ret) { if (ret) {
dev_err(pctrl->dev, "failed to add irqchip\n"); dev_err(pctrl->dev, "failed to add irqchip\n");
return ret; return ret;
} }
gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq, gpiochip_set_chained_irqchip(&pctrl->chip, &pctrl->irqchip, irq, NULL);
NULL);
return 0; return 0;
} }

26
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
View File

@ -183,10 +183,10 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19), PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19), BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
18, 2, "gpio", "uart"), 18, 2, "gpio", "uart"),
PIN_GRP_GPIO("led0_od", 11, 1, BIT(20), "led"), PIN_GRP_GPIO_2("led0_od", 11, 1, BIT(20), BIT(20), 0, "led"),
PIN_GRP_GPIO("led1_od", 12, 1, BIT(21), "led"), PIN_GRP_GPIO_2("led1_od", 12, 1, BIT(21), BIT(21), 0, "led"),
PIN_GRP_GPIO("led2_od", 13, 1, BIT(22), "led"), PIN_GRP_GPIO_2("led2_od", 13, 1, BIT(22), BIT(22), 0, "led"),
PIN_GRP_GPIO("led3_od", 14, 1, BIT(23), "led"), PIN_GRP_GPIO_2("led3_od", 14, 1, BIT(23), BIT(23), 0, "led"),
}; };
@ -221,11 +221,11 @@ static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
}; };
static inline void armada_37xx_update_reg(unsigned int *reg, static inline void armada_37xx_update_reg(unsigned int *reg,
unsigned int offset) unsigned int *offset)
{ {
/* We never have more than 2 registers */ /* We never have more than 2 registers */
if (offset >= GPIO_PER_REG) { if (*offset >= GPIO_PER_REG) {
offset -= GPIO_PER_REG; *offset -= GPIO_PER_REG;
*reg += sizeof(u32); *reg += sizeof(u32);
} }
} }
@ -376,7 +376,7 @@ static inline void armada_37xx_irq_update_reg(unsigned int *reg,
{ {
int offset = irqd_to_hwirq(d); int offset = irqd_to_hwirq(d);
armada_37xx_update_reg(reg, offset); armada_37xx_update_reg(reg, &offset);
} }
static int armada_37xx_gpio_direction_input(struct gpio_chip *chip, static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
@ -386,7 +386,7 @@ static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
unsigned int reg = OUTPUT_EN; unsigned int reg = OUTPUT_EN;
unsigned int mask; unsigned int mask;
armada_37xx_update_reg(&reg, offset); armada_37xx_update_reg(&reg, &offset);
mask = BIT(offset); mask = BIT(offset);
return regmap_update_bits(info->regmap, reg, mask, 0); return regmap_update_bits(info->regmap, reg, mask, 0);
@ -399,7 +399,7 @@ static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
unsigned int reg = OUTPUT_EN; unsigned int reg = OUTPUT_EN;
unsigned int val, mask; unsigned int val, mask;
armada_37xx_update_reg(&reg, offset); armada_37xx_update_reg(&reg, &offset);
mask = BIT(offset); mask = BIT(offset);
regmap_read(info->regmap, reg, &val); regmap_read(info->regmap, reg, &val);
@ -413,7 +413,7 @@ static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
unsigned int reg = OUTPUT_EN; unsigned int reg = OUTPUT_EN;
unsigned int mask, val, ret; unsigned int mask, val, ret;
armada_37xx_update_reg(&reg, offset); armada_37xx_update_reg(&reg, &offset);
mask = BIT(offset); mask = BIT(offset);
ret = regmap_update_bits(info->regmap, reg, mask, mask); ret = regmap_update_bits(info->regmap, reg, mask, mask);
@ -434,7 +434,7 @@ static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
unsigned int reg = INPUT_VAL; unsigned int reg = INPUT_VAL;
unsigned int val, mask; unsigned int val, mask;
armada_37xx_update_reg(&reg, offset); armada_37xx_update_reg(&reg, &offset);
mask = BIT(offset); mask = BIT(offset);
regmap_read(info->regmap, reg, &val); regmap_read(info->regmap, reg, &val);
@ -449,7 +449,7 @@ static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
unsigned int reg = OUTPUT_VAL; unsigned int reg = OUTPUT_VAL;
unsigned int mask, val; unsigned int mask, val;
armada_37xx_update_reg(&reg, offset); armada_37xx_update_reg(&reg, &offset);
mask = BIT(offset); mask = BIT(offset);
val = value ? mask : 0; val = value ? mask : 0;

2
drivers/pinctrl/pinctrl-stmfx.c
View File

@ -705,7 +705,7 @@ static int stmfx_pinctrl_probe(struct platform_device *pdev)
static int stmfx_pinctrl_remove(struct platform_device *pdev) static int stmfx_pinctrl_remove(struct platform_device *pdev)
{ {
struct stmfx *stmfx = dev_get_platdata(&pdev->dev); struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent);
return stmfx_function_disable(stmfx, return stmfx_function_disable(stmfx,
STMFX_FUNC_GPIO | STMFX_FUNC_GPIO |