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clk: socfpga: stratix10: add additional clocks needed for the NAND IP 

The nand_clk is actually called the nand_x_clk and the parent is the
l4_mp_clk, not the l4_main_clk. The nand_clk is a child of the
nand_x_clk and has a fixed divider of 4. The same is true for the
nand_ecc_clk.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Dinh Nguyen 2019-06-24 16:47:10 -05:00 committed by Stephen Boyd
parent a188339ca5
commit 3b5015c4d8
2 changed files with 8 additions and 2 deletions
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6
drivers/clk/socfpga/clk-s10.c
View File

@ -161,8 +161,12 @@ static const struct stratix10_gate_clock s10_gate_clks[] = {
8, 0, 0, 0, 0, 0, 0},
{ STRATIX10_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0xA4,
9, 0, 0, 0, 0, 0, 0},
{ STRATIX10_NAND_CLK, "nand_clk", "l4_main_clk", NULL, 1, 0, 0xA4,
{ STRATIX10_NAND_X_CLK, "nand_x_clk", "l4_mp_clk", NULL, 1, 0, 0xA4,
10, 0, 0, 0, 0, 0, 0},
{ STRATIX10_NAND_CLK, "nand_clk", "nand_x_clk", NULL, 1, 0, 0xA4,
10, 0, 0, 0, 0, 0, 4},
{ STRATIX10_NAND_ECC_CLK, "nand_ecc_clk", "nand_x_clk", NULL, 1, 0, 0xA4,
10, 0, 0, 0, 0, 0, 4},
};
static int s10_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,

4
include/dt-bindings/clock/stratix10-clock.h
View File

@ -79,6 +79,8 @@
#define STRATIX10_USB_CLK 59
#define STRATIX10_SPI_M_CLK 60
#define STRATIX10_NAND_CLK 61
#define STRATIX10_NUM_CLKS 62
#define STRATIX10_NAND_X_CLK 62
#define STRATIX10_NAND_ECC_CLK 63
#define STRATIX10_NUM_CLKS 64
#endif /* __STRATIX10_CLOCK_H */