LoongArch: KVM: Add IPI read and write function
Upstream: no Implementation of IPI interrupt controller address space read and write function simulation. Signed-off-by: Min Zhou <zhoumin@loongson.cn> Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
This commit is contained in:
Xianglai Li
parent
ec9365931f
commit
3b3a64fa1c
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@ -39,6 +39,8 @@ struct kvm_vm_stat {
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struct kvm_vm_stat_generic generic;
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u64 pages;
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u64 hugepages;
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u64 ipi_read_exits;
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u64 ipi_write_exits;
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};
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struct kvm_vcpu_stat {
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@ -29,8 +29,24 @@ struct ipi_state {
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#define SMP_MAILBOX 0x1000
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#define KVM_IOCSR_IPI_ADDR_SIZE 0x48
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#define CORE_STATUS_OFF 0x000
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#define CORE_EN_OFF 0x004
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#define CORE_SET_OFF 0x008
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#define CORE_CLEAR_OFF 0x00c
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#define CORE_BUF_20 0x020
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#define CORE_BUF_28 0x028
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#define CORE_BUF_30 0x030
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#define CORE_BUF_38 0x038
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#define IOCSR_IPI_SEND 0x040
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#define IOCSR_MAIL_SEND 0x048
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#define IOCSR_ANY_SEND 0x158
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#define MAIL_SEND_ADDR (SMP_MAILBOX + IOCSR_MAIL_SEND)
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#define KVM_IOCSR_MAIL_ADDR_SIZE 0x118
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#define MAIL_SEND_OFFSET 0
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#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
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int kvm_loongarch_register_ipi_device(void);
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#endif
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@ -7,24 +7,307 @@
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#include <asm/kvm_ipi.h>
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#include <asm/kvm_vcpu.h>
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static void ipi_send(struct kvm *kvm, uint64_t data)
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{
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struct kvm_vcpu *vcpu;
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struct kvm_interrupt irq;
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int cpu, action, status;
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cpu = ((data & 0xffffffff) >> 16) & 0x3ff;
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vcpu = kvm_get_vcpu_by_cpuid(kvm, cpu);
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if (unlikely(vcpu == NULL)) {
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kvm_err("%s: invalid target cpu: %d\n", __func__, cpu);
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return;
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}
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action = 1 << (data & 0x1f);
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spin_lock(&vcpu->arch.ipi_state.lock);
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status = vcpu->arch.ipi_state.status;
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vcpu->arch.ipi_state.status |= action;
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if (status == 0) {
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irq.irq = LARCH_INT_IPI;
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kvm_vcpu_ioctl_interrupt(vcpu, &irq);
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}
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spin_unlock(&vcpu->arch.ipi_state.lock);
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}
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static void ipi_clear(struct kvm_vcpu *vcpu, uint64_t data)
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{
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struct kvm_interrupt irq;
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spin_lock(&vcpu->arch.ipi_state.lock);
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vcpu->arch.ipi_state.status &= ~data;
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if (!vcpu->arch.ipi_state.status) {
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irq.irq = -LARCH_INT_IPI;
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kvm_vcpu_ioctl_interrupt(vcpu, &irq);
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}
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spin_unlock(&vcpu->arch.ipi_state.lock);
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}
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static uint64_t read_mailbox(struct kvm_vcpu *vcpu, int offset, int len)
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{
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void *pbuf;
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uint64_t ret = 0;
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spin_lock(&vcpu->arch.ipi_state.lock);
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pbuf = (void *)vcpu->arch.ipi_state.buf + (offset - 0x20);
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if (len == 1)
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ret = *(unsigned char *)pbuf;
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else if (len == 2)
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ret = *(unsigned short *)pbuf;
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else if (len == 4)
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ret = *(unsigned int *)pbuf;
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else if (len == 8)
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ret = *(unsigned long *)pbuf;
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else
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kvm_err("%s: unknown data len: %d\n", __func__, len);
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spin_unlock(&vcpu->arch.ipi_state.lock);
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return ret;
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}
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static void write_mailbox(struct kvm_vcpu *vcpu, int offset,
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uint64_t data, int len)
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{
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void *pbuf;
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spin_lock(&vcpu->arch.ipi_state.lock);
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pbuf = (void *)vcpu->arch.ipi_state.buf + (offset - 0x20);
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if (len == 1)
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*(unsigned char *)pbuf = (unsigned char)data;
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else if (len == 2)
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*(unsigned short *)pbuf = (unsigned short)data;
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else if (len == 4)
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*(unsigned int *)pbuf = (unsigned int)data;
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else if (len == 8)
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*(unsigned long *)pbuf = (unsigned long)data;
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else
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kvm_err("%s: unknown data len: %d\n", __func__, len);
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spin_unlock(&vcpu->arch.ipi_state.lock);
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}
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static int loongarch_ipi_writel(struct kvm_vcpu *vcpu, gpa_t addr,
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int len, const void *val)
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{
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uint64_t data;
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uint32_t offset;
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int ret = 0;
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data = *(uint64_t *)val;
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offset = (uint32_t)(addr & 0xff);
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WARN_ON_ONCE(offset & (len - 1));
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switch (offset) {
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case CORE_STATUS_OFF:
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kvm_err("CORE_SET_OFF Can't be write\n");
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ret = -EINVAL;
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break;
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case CORE_EN_OFF:
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spin_lock(&vcpu->arch.ipi_state.lock);
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vcpu->arch.ipi_state.en = data;
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spin_unlock(&vcpu->arch.ipi_state.lock);
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break;
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case IOCSR_IPI_SEND:
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ipi_send(vcpu->kvm, data);
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break;
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case CORE_SET_OFF:
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kvm_info("CORE_SET_OFF simulation is required\n");
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ret = -EINVAL;
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break;
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case CORE_CLEAR_OFF:
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/* Just clear the status of the current vcpu */
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ipi_clear(vcpu, data);
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break;
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case CORE_BUF_20 ... CORE_BUF_38 + 7:
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if (offset + len > CORE_BUF_38 + 8) {
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kvm_err("%s: invalid offset or len: offset = %d, len = %d\n",
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__func__, offset, len);
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ret = -EINVAL;
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break;
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}
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write_mailbox(vcpu, offset, data, len);
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break;
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default:
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kvm_err("%s: unknown addr: %llx\n", __func__, addr);
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static int loongarch_ipi_readl(struct kvm_vcpu *vcpu, gpa_t addr,
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int len, void *val)
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{
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uint32_t offset;
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uint64_t res = 0;
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int ret = 0;
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offset = (uint32_t)(addr & 0xff);
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WARN_ON_ONCE(offset & (len - 1));
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switch (offset) {
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case CORE_STATUS_OFF:
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spin_lock(&vcpu->arch.ipi_state.lock);
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res = vcpu->arch.ipi_state.status;
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spin_unlock(&vcpu->arch.ipi_state.lock);
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break;
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case CORE_EN_OFF:
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spin_lock(&vcpu->arch.ipi_state.lock);
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res = vcpu->arch.ipi_state.en;
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spin_unlock(&vcpu->arch.ipi_state.lock);
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break;
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case CORE_SET_OFF:
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res = 0;
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break;
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case CORE_CLEAR_OFF:
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res = 0;
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break;
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case CORE_BUF_20 ... CORE_BUF_38 + 7:
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if (offset + len > CORE_BUF_38 + 8) {
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kvm_err("%s: invalid offset or len: offset = %d, len = %d\n",
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__func__, offset, len);
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ret = -EINVAL;
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break;
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}
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res = read_mailbox(vcpu, offset, len);
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break;
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default:
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kvm_err("%s: unknown addr: %llx\n", __func__, addr);
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ret = -EINVAL;
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break;
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}
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*(uint64_t *)val = res;
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return ret;
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}
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static int kvm_loongarch_ipi_write(struct kvm_vcpu *vcpu,
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struct kvm_io_device *dev,
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gpa_t addr, int len, const void *val)
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{
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return 0;
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struct loongarch_ipi *ipi;
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int ret;
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ipi = vcpu->kvm->arch.ipi;
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if (!ipi) {
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kvm_err("%s: ipi irqchip not valid!\n", __func__);
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return -EINVAL;
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}
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ipi->kvm->stat.ipi_write_exits++;
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ret = loongarch_ipi_writel(vcpu, addr, len, val);
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return ret;
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}
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static int kvm_loongarch_ipi_read(struct kvm_vcpu *vcpu,
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struct kvm_io_device *dev,
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gpa_t addr, int len, void *val)
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{
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return 0;
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struct loongarch_ipi *ipi;
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int ret;
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ipi = vcpu->kvm->arch.ipi;
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if (!ipi) {
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kvm_err("%s: ipi irqchip not valid!\n", __func__);
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return -EINVAL;
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}
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ipi->kvm->stat.ipi_read_exits++;
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ret = loongarch_ipi_readl(vcpu, addr, len, val);
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return ret;
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}
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static void send_ipi_data(struct kvm_vcpu *vcpu, gpa_t addr, uint64_t data)
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{
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int i;
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uint32_t val = 0, mask = 0;
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/*
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* Bit 27-30 is mask for byte writing.
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* If the mask is 0, we need not to do anything.
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*/
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if ((data >> 27) & 0xf) {
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/* Read the old val */
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kvm_io_bus_read(vcpu, KVM_IOCSR_BUS, addr, sizeof(val), &val);
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/* Construct the mask by scanning the bit 27-30 */
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for (i = 0; i < 4; i++) {
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if (data & (0x1 << (27 + i)))
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mask |= (0xff << (i * 8));
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}
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/* Save the old part of val */
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val &= mask;
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}
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val |= ((uint32_t)(data >> 32) & ~mask);
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kvm_io_bus_write(vcpu, KVM_IOCSR_BUS, addr, sizeof(val), &val);
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}
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static void mail_send(struct kvm *kvm, uint64_t data)
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{
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struct kvm_vcpu *vcpu;
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int cpu, mailbox;
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int offset;
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cpu = ((data & 0xffffffff) >> 16) & 0x3ff;
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vcpu = kvm_get_vcpu_by_cpuid(kvm, cpu);
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if (unlikely(vcpu == NULL)) {
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kvm_err("%s: invalid target cpu: %d\n", __func__, cpu);
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return;
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}
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mailbox = ((data & 0xffffffff) >> 2) & 0x7;
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offset = SMP_MAILBOX + CORE_BUF_20 + mailbox * 4;
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send_ipi_data(vcpu, offset, data);
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}
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static void any_send(struct kvm *kvm, uint64_t data)
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{
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struct kvm_vcpu *vcpu;
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int cpu, offset;
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cpu = ((data & 0xffffffff) >> 16) & 0x3ff;
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vcpu = kvm_get_vcpu_by_cpuid(kvm, cpu);
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if (unlikely(vcpu == NULL)) {
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kvm_err("%s: invalid target cpu: %d\n", __func__, cpu);
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return;
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}
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offset = data & 0xffff;
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send_ipi_data(vcpu, offset, data);
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}
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static int kvm_loongarch_mail_write(struct kvm_vcpu *vcpu,
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struct kvm_io_device *dev,
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gpa_t addr, int len, const void *val)
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{
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struct loongarch_ipi *ipi;
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ipi = vcpu->kvm->arch.ipi;
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if (!ipi) {
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kvm_err("%s: ipi irqchip not valid!\n", __func__);
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return -EINVAL;
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}
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addr &= 0xfff;
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addr -= IOCSR_MAIL_SEND;
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switch (addr) {
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case MAIL_SEND_OFFSET:
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mail_send(vcpu->kvm, *(uint64_t *)val);
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break;
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case ANY_SEND_OFFSET:
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any_send(vcpu->kvm, *(uint64_t *)val);
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break;
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default:
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break;
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}
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return 0;
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}
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