- Add DT binding documentation to support the r8a7742 and r8a774e1
platforms (Lad Prabhakar) - Add sp804 variant support for the Hisilicon platforms (Kefeng Wang) -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEGn3N4YVz0WNVyHskqDIjiipP6E8FAl9sYMgACgkQqDIjiipP 6E9sLQf/WBzAhpPO8H5zSxuf5Z1XzwRRWxvPA/x46Td3HRszl8ep4RR8d88wh2My EjnZ+UNPxY6aIc76e16Hy+KDKvfpVP6OrswAMhTKbB8meb+qVQPQ6Tf8AkpbOhKo DDUHIUQ3QzUxhy99d2NB0vA8H3FBtqdxa0RM/WMaIHCm1+1y9kmGHD59EE39opGM hbBM7WDPNu0lG5E12wfLGDGrP7KJudHZgCfBR5Fb8uxq+GFGWYSWoQP/nTy9Ubht MuIN4fVBAaUB+SecxG8BvcFVXMevuC+vQdrxjtueWxgVBGzVxNH3rydIHN2AJC98 LZ1Kzg0Y/FIr+OL4w9LAo2IXSymEpg== =ZvdN -----END PGP SIGNATURE----- Merge tag 'timers-v5.10' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core Pull clocksource/event updates from Daniel Lezcano: - Add DT binding documentation to support the r8a7742 and r8a774e1 platforms (Lad Prabhakar) - Add sp804 variant support for the Hisilicon platforms (Kefeng Wang)
This commit is contained in:
Thomas Gleixner
commit
3b17c8f9a4
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@ -39,6 +39,7 @@ properties:
|
|||
- items:
|
||||
- enum:
|
||||
- renesas,r8a73a4-cmt0 # 32-bit CMT0 on R-Mobile APE6
|
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- renesas,r8a7742-cmt0 # 32-bit CMT0 on RZ/G1H
|
||||
- renesas,r8a7743-cmt0 # 32-bit CMT0 on RZ/G1M
|
||||
- renesas,r8a7744-cmt0 # 32-bit CMT0 on RZ/G1N
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- renesas,r8a7745-cmt0 # 32-bit CMT0 on RZ/G1E
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||||
|
|
@ -53,6 +54,7 @@ properties:
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- items:
|
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- enum:
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||||
- renesas,r8a73a4-cmt1 # 48-bit CMT1 on R-Mobile APE6
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||||
- renesas,r8a7742-cmt1 # 48-bit CMT1 on RZ/G1H
|
||||
- renesas,r8a7743-cmt1 # 48-bit CMT1 on RZ/G1M
|
||||
- renesas,r8a7744-cmt1 # 48-bit CMT1 on RZ/G1N
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- renesas,r8a7745-cmt1 # 48-bit CMT1 on RZ/G1E
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|
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@ -69,6 +71,7 @@ properties:
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- renesas,r8a774a1-cmt0 # 32-bit CMT0 on RZ/G2M
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- renesas,r8a774b1-cmt0 # 32-bit CMT0 on RZ/G2N
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- renesas,r8a774c0-cmt0 # 32-bit CMT0 on RZ/G2E
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- renesas,r8a774e1-cmt0 # 32-bit CMT0 on RZ/G2H
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- renesas,r8a7795-cmt0 # 32-bit CMT0 on R-Car H3
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- renesas,r8a7796-cmt0 # 32-bit CMT0 on R-Car M3-W
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- renesas,r8a77965-cmt0 # 32-bit CMT0 on R-Car M3-N
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|
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@ -83,6 +86,7 @@ properties:
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- renesas,r8a774a1-cmt1 # 48-bit CMT on RZ/G2M
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||||
- renesas,r8a774b1-cmt1 # 48-bit CMT on RZ/G2N
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||||
- renesas,r8a774c0-cmt1 # 48-bit CMT on RZ/G2E
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||||
- renesas,r8a774e1-cmt1 # 48-bit CMT on RZ/G2H
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||||
- renesas,r8a7795-cmt1 # 48-bit CMT on R-Car H3
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- renesas,r8a7796-cmt1 # 48-bit CMT on R-Car M3-W
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- renesas,r8a77965-cmt1 # 48-bit CMT on R-Car M3-N
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@ -10,6 +10,7 @@
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*
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* Every SP804 contains two identical timers.
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*/
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#define NR_TIMERS 2
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#define TIMER_1_BASE 0x00
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#define TIMER_2_BASE 0x20
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@ -29,3 +30,34 @@
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#define TIMER_RIS 0x10 /* CVR ro */
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#define TIMER_MIS 0x14 /* CVR ro */
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#define TIMER_BGLOAD 0x18 /* CVR rw */
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struct sp804_timer {
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int load;
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int load_h;
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int value;
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int value_h;
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int ctrl;
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int intclr;
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int ris;
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int mis;
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int bgload;
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int bgload_h;
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int timer_base[NR_TIMERS];
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int width;
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};
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struct sp804_clkevt {
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void __iomem *base;
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void __iomem *load;
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void __iomem *load_h;
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void __iomem *value;
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void __iomem *value_h;
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void __iomem *ctrl;
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void __iomem *intclr;
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void __iomem *ris;
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void __iomem *mis;
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void __iomem *bgload;
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void __iomem *bgload_h;
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unsigned long reload;
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int width;
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};
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@ -18,15 +18,57 @@
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#include <linux/of_irq.h>
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#include <linux/sched_clock.h>
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#include <clocksource/timer-sp804.h>
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#include "timer-sp.h"
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static long __init sp804_get_clock_rate(struct clk *clk)
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/* Hisilicon 64-bit timer(a variant of ARM SP804) */
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#define HISI_TIMER_1_BASE 0x00
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#define HISI_TIMER_2_BASE 0x40
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#define HISI_TIMER_LOAD 0x00
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#define HISI_TIMER_LOAD_H 0x04
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#define HISI_TIMER_VALUE 0x08
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#define HISI_TIMER_VALUE_H 0x0c
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#define HISI_TIMER_CTRL 0x10
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#define HISI_TIMER_INTCLR 0x14
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#define HISI_TIMER_RIS 0x18
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#define HISI_TIMER_MIS 0x1c
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#define HISI_TIMER_BGLOAD 0x20
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#define HISI_TIMER_BGLOAD_H 0x24
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struct sp804_timer __initdata arm_sp804_timer = {
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.load = TIMER_LOAD,
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.value = TIMER_VALUE,
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.ctrl = TIMER_CTRL,
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.intclr = TIMER_INTCLR,
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.timer_base = {TIMER_1_BASE, TIMER_2_BASE},
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.width = 32,
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};
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struct sp804_timer __initdata hisi_sp804_timer = {
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.load = HISI_TIMER_LOAD,
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.load_h = HISI_TIMER_LOAD_H,
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.value = HISI_TIMER_VALUE,
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.value_h = HISI_TIMER_VALUE_H,
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.ctrl = HISI_TIMER_CTRL,
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.intclr = HISI_TIMER_INTCLR,
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.timer_base = {HISI_TIMER_1_BASE, HISI_TIMER_2_BASE},
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.width = 64,
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};
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static struct sp804_clkevt sp804_clkevt[NR_TIMERS];
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static long __init sp804_get_clock_rate(struct clk *clk, const char *name)
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{
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long rate;
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int err;
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if (!clk)
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clk = clk_get_sys("sp804", name);
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if (IS_ERR(clk)) {
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pr_err("sp804: %s clock not found: %ld\n", name, PTR_ERR(clk));
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return PTR_ERR(clk);
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}
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err = clk_prepare(clk);
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if (err) {
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pr_err("sp804: clock failed to prepare: %d\n", err);
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@ -53,50 +95,57 @@ static long __init sp804_get_clock_rate(struct clk *clk)
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return rate;
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}
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static void __iomem *sched_clock_base;
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static struct sp804_clkevt * __init sp804_clkevt_get(void __iomem *base)
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{
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int i;
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for (i = 0; i < NR_TIMERS; i++) {
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if (sp804_clkevt[i].base == base)
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return &sp804_clkevt[i];
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}
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/* It's impossible to reach here */
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WARN_ON(1);
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return NULL;
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}
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static struct sp804_clkevt *sched_clkevt;
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static u64 notrace sp804_read(void)
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{
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return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
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return ~readl_relaxed(sched_clkevt->value);
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}
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void __init sp804_timer_disable(void __iomem *base)
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{
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writel(0, base + TIMER_CTRL);
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}
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int __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
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const char *name,
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struct clk *clk,
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int use_sched_clock)
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int __init sp804_clocksource_and_sched_clock_init(void __iomem *base,
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const char *name,
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struct clk *clk,
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int use_sched_clock)
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{
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long rate;
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struct sp804_clkevt *clkevt;
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if (!clk) {
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clk = clk_get_sys("sp804", name);
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if (IS_ERR(clk)) {
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pr_err("sp804: clock not found: %d\n",
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(int)PTR_ERR(clk));
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return PTR_ERR(clk);
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}
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}
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rate = sp804_get_clock_rate(clk);
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rate = sp804_get_clock_rate(clk, name);
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if (rate < 0)
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return -EINVAL;
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/* setup timer 0 as free-running clocksource */
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writel(0, base + TIMER_CTRL);
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writel(0xffffffff, base + TIMER_LOAD);
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writel(0xffffffff, base + TIMER_VALUE);
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writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
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base + TIMER_CTRL);
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clkevt = sp804_clkevt_get(base);
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clocksource_mmio_init(base + TIMER_VALUE, name,
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writel(0, clkevt->ctrl);
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writel(0xffffffff, clkevt->load);
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writel(0xffffffff, clkevt->value);
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if (clkevt->width == 64) {
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writel(0xffffffff, clkevt->load_h);
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writel(0xffffffff, clkevt->value_h);
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}
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writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
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clkevt->ctrl);
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clocksource_mmio_init(clkevt->value, name,
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rate, 200, 32, clocksource_mmio_readl_down);
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if (use_sched_clock) {
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sched_clock_base = base;
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sched_clkevt = clkevt;
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sched_clock_register(sp804_read, 32, rate);
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}
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@ -104,8 +153,7 @@ int __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
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}
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static void __iomem *clkevt_base;
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static unsigned long clkevt_reload;
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static struct sp804_clkevt *common_clkevt;
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/*
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* IRQ handler for the timer
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@ -115,7 +163,7 @@ static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
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struct clock_event_device *evt = dev_id;
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/* clear the interrupt */
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writel(1, clkevt_base + TIMER_INTCLR);
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writel(1, common_clkevt->intclr);
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evt->event_handler(evt);
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@ -124,7 +172,7 @@ static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
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static inline void timer_shutdown(struct clock_event_device *evt)
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{
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writel(0, clkevt_base + TIMER_CTRL);
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writel(0, common_clkevt->ctrl);
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}
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static int sp804_shutdown(struct clock_event_device *evt)
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@ -139,8 +187,8 @@ static int sp804_set_periodic(struct clock_event_device *evt)
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TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
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|
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timer_shutdown(evt);
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writel(clkevt_reload, clkevt_base + TIMER_LOAD);
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writel(ctrl, clkevt_base + TIMER_CTRL);
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writel(common_clkevt->reload, common_clkevt->load);
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writel(ctrl, common_clkevt->ctrl);
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return 0;
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}
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|
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@ -150,8 +198,8 @@ static int sp804_set_next_event(unsigned long next,
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unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE |
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TIMER_CTRL_ONESHOT | TIMER_CTRL_ENABLE;
|
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|
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writel(next, clkevt_base + TIMER_LOAD);
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writel(ctrl, clkevt_base + TIMER_CTRL);
|
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writel(next, common_clkevt->load);
|
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writel(ctrl, common_clkevt->ctrl);
|
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|
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return 0;
|
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}
|
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|
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@ -168,30 +216,23 @@ static struct clock_event_device sp804_clockevent = {
|
|||
.rating = 300,
|
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};
|
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|
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int __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct clk *clk, const char *name)
|
||||
int __init sp804_clockevents_init(void __iomem *base, unsigned int irq,
|
||||
struct clk *clk, const char *name)
|
||||
{
|
||||
struct clock_event_device *evt = &sp804_clockevent;
|
||||
long rate;
|
||||
|
||||
if (!clk)
|
||||
clk = clk_get_sys("sp804", name);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("sp804: %s clock not found: %d\n", name,
|
||||
(int)PTR_ERR(clk));
|
||||
return PTR_ERR(clk);
|
||||
}
|
||||
|
||||
rate = sp804_get_clock_rate(clk);
|
||||
rate = sp804_get_clock_rate(clk, name);
|
||||
if (rate < 0)
|
||||
return -EINVAL;
|
||||
|
||||
clkevt_base = base;
|
||||
clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ);
|
||||
common_clkevt = sp804_clkevt_get(base);
|
||||
common_clkevt->reload = DIV_ROUND_CLOSEST(rate, HZ);
|
||||
evt->name = name;
|
||||
evt->irq = irq;
|
||||
evt->cpumask = cpu_possible_mask;
|
||||
|
||||
writel(0, base + TIMER_CTRL);
|
||||
writel(0, common_clkevt->ctrl);
|
||||
|
||||
if (request_irq(irq, sp804_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
|
||||
"timer", &sp804_clockevent))
|
||||
|
|
@ -201,10 +242,33 @@ int __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int __init sp804_of_init(struct device_node *np)
|
||||
static void __init sp804_clkevt_init(struct sp804_timer *timer, void __iomem *base)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < NR_TIMERS; i++) {
|
||||
void __iomem *timer_base;
|
||||
struct sp804_clkevt *clkevt;
|
||||
|
||||
timer_base = base + timer->timer_base[i];
|
||||
clkevt = &sp804_clkevt[i];
|
||||
clkevt->base = timer_base;
|
||||
clkevt->load = timer_base + timer->load;
|
||||
clkevt->load_h = timer_base + timer->load_h;
|
||||
clkevt->value = timer_base + timer->value;
|
||||
clkevt->value_h = timer_base + timer->value_h;
|
||||
clkevt->ctrl = timer_base + timer->ctrl;
|
||||
clkevt->intclr = timer_base + timer->intclr;
|
||||
clkevt->width = timer->width;
|
||||
}
|
||||
}
|
||||
|
||||
static int __init sp804_of_init(struct device_node *np, struct sp804_timer *timer)
|
||||
{
|
||||
static bool initialized = false;
|
||||
void __iomem *base;
|
||||
void __iomem *timer1_base;
|
||||
void __iomem *timer2_base;
|
||||
int irq, ret = -EINVAL;
|
||||
u32 irq_num = 0;
|
||||
struct clk *clk1, *clk2;
|
||||
|
|
@ -214,9 +278,12 @@ static int __init sp804_of_init(struct device_node *np)
|
|||
if (!base)
|
||||
return -ENXIO;
|
||||
|
||||
timer1_base = base + timer->timer_base[0];
|
||||
timer2_base = base + timer->timer_base[1];
|
||||
|
||||
/* Ensure timers are disabled */
|
||||
writel(0, base + TIMER_CTRL);
|
||||
writel(0, base + TIMER_2_BASE + TIMER_CTRL);
|
||||
writel(0, timer1_base + timer->ctrl);
|
||||
writel(0, timer2_base + timer->ctrl);
|
||||
|
||||
if (initialized || !of_device_is_available(np)) {
|
||||
ret = -EINVAL;
|
||||
|
|
@ -242,24 +309,27 @@ static int __init sp804_of_init(struct device_node *np)
|
|||
if (irq <= 0)
|
||||
goto err;
|
||||
|
||||
sp804_clkevt_init(timer, base);
|
||||
|
||||
of_property_read_u32(np, "arm,sp804-has-irq", &irq_num);
|
||||
if (irq_num == 2) {
|
||||
|
||||
ret = __sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name);
|
||||
ret = sp804_clockevents_init(timer2_base, irq, clk2, name);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
ret = __sp804_clocksource_and_sched_clock_init(base, name, clk1, 1);
|
||||
ret = sp804_clocksource_and_sched_clock_init(timer1_base,
|
||||
name, clk1, 1);
|
||||
if (ret)
|
||||
goto err;
|
||||
} else {
|
||||
|
||||
ret = __sp804_clockevents_init(base, irq, clk1 , name);
|
||||
ret = sp804_clockevents_init(timer1_base, irq, clk1, name);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
ret =__sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE,
|
||||
name, clk2, 1);
|
||||
ret = sp804_clocksource_and_sched_clock_init(timer2_base,
|
||||
name, clk2, 1);
|
||||
if (ret)
|
||||
goto err;
|
||||
}
|
||||
|
|
@ -270,7 +340,18 @@ err:
|
|||
iounmap(base);
|
||||
return ret;
|
||||
}
|
||||
TIMER_OF_DECLARE(sp804, "arm,sp804", sp804_of_init);
|
||||
|
||||
static int __init arm_sp804_of_init(struct device_node *np)
|
||||
{
|
||||
return sp804_of_init(np, &arm_sp804_timer);
|
||||
}
|
||||
TIMER_OF_DECLARE(sp804, "arm,sp804", arm_sp804_of_init);
|
||||
|
||||
static int __init hisi_sp804_of_init(struct device_node *np)
|
||||
{
|
||||
return sp804_of_init(np, &hisi_sp804_timer);
|
||||
}
|
||||
TIMER_OF_DECLARE(hisi_sp804, "hisilicon,sp804", hisi_sp804_of_init);
|
||||
|
||||
static int __init integrator_cp_of_init(struct device_node *np)
|
||||
{
|
||||
|
|
@ -293,13 +374,16 @@ static int __init integrator_cp_of_init(struct device_node *np)
|
|||
}
|
||||
|
||||
/* Ensure timer is disabled */
|
||||
writel(0, base + TIMER_CTRL);
|
||||
writel(0, base + arm_sp804_timer.ctrl);
|
||||
|
||||
if (init_count == 2 || !of_device_is_available(np))
|
||||
goto err;
|
||||
|
||||
sp804_clkevt_init(&arm_sp804_timer, base);
|
||||
|
||||
if (!init_count) {
|
||||
ret = __sp804_clocksource_and_sched_clock_init(base, name, clk, 0);
|
||||
ret = sp804_clocksource_and_sched_clock_init(base,
|
||||
name, clk, 0);
|
||||
if (ret)
|
||||
goto err;
|
||||
} else {
|
||||
|
|
@ -307,7 +391,7 @@ static int __init integrator_cp_of_init(struct device_node *np)
|
|||
if (irq <= 0)
|
||||
goto err;
|
||||
|
||||
ret = __sp804_clockevents_init(base, irq, clk, name);
|
||||
ret = sp804_clockevents_init(base, irq, clk, name);
|
||||
if (ret)
|
||||
goto err;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,29 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __CLKSOURCE_TIMER_SP804_H
|
||||
#define __CLKSOURCE_TIMER_SP804_H
|
||||
|
||||
struct clk;
|
||||
|
||||
int __sp804_clocksource_and_sched_clock_init(void __iomem *,
|
||||
const char *, struct clk *, int);
|
||||
int __sp804_clockevents_init(void __iomem *, unsigned int,
|
||||
struct clk *, const char *);
|
||||
void sp804_timer_disable(void __iomem *);
|
||||
|
||||
static inline void sp804_clocksource_init(void __iomem *base, const char *name)
|
||||
{
|
||||
__sp804_clocksource_and_sched_clock_init(base, name, NULL, 0);
|
||||
}
|
||||
|
||||
static inline void sp804_clocksource_and_sched_clock_init(void __iomem *base,
|
||||
const char *name)
|
||||
{
|
||||
__sp804_clocksource_and_sched_clock_init(base, name, NULL, 1);
|
||||
}
|
||||
|
||||
static inline void sp804_clockevents_init(void __iomem *base, unsigned int irq, const char *name)
|
||||
{
|
||||
__sp804_clockevents_init(base, irq, NULL, name);
|
||||
|
||||
}
|
||||
#endif
|
||||
Loading…
Reference in New Issue