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ASoC: fsl_micfil: change micfil default settings 

Previous default settings resulted in loose dynamic
range and low sound level.
New default configuration changes:
- outgain = 2
- quality mode = VLOW0
- dc remover = bypass

Signed-off-by: Irina Patru <ioana-irina.patru@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link: https://lore.kernel.org/r/1656405589-29850-1-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Shengjiu Wang 2022-06-28 16:39:49 +08:00 committed by Mark Brown
parent d29e0a6e36
commit 3b13b1437d
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
2 changed files with 27 additions and 4 deletions
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22
sound/soc/fsl/fsl_micfil.c
View File

@ -48,6 +48,7 @@ struct fsl_micfil {
char name[32];
int irq[MICFIL_IRQ_LINES];
enum quality quality;
int dc_remover;
};
struct fsl_micfil_soc_data {
@ -317,12 +318,25 @@ static const struct snd_soc_dai_ops fsl_micfil_dai_ops = {
static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
{
struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
int ret;
struct device *dev = cpu_dai->dev;
unsigned int val = 0;
int ret, i;
micfil->quality = QUALITY_MEDIUM;
micfil->quality = QUALITY_VLOW0;
/* set default gain to max_gain */
regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x77777777);
/* set default gain to 2 */
regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x22222222);
/* set DC Remover in bypass mode*/
for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)
val |= MICFIL_DC_BYPASS << MICFIL_DC_CHX_SHIFT(i);
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_DC_CTRL,
MICFIL_DC_CTRL_CONFIG, val);
if (ret) {
dev_err(dev, "failed to set DC Remover mode bits\n");
return ret;
}
micfil->dc_remover = MICFIL_DC_BYPASS;
snd_soc_dai_init_dma_data(cpu_dai, NULL,
&micfil->dma_params_rx);

9
sound/soc/fsl/fsl_micfil.h
View File

@ -73,6 +73,15 @@
#define MICFIL_FIFO_STAT_FIFOX_OVER(ch) BIT(ch)
#define MICFIL_FIFO_STAT_FIFOX_UNDER(ch) BIT((ch) + 8)
/* MICFIL DC Remover Control Register -- REG_MICFIL_DC_CTRL */
#define MICFIL_DC_CTRL_CONFIG GENMASK(15, 0)
#define MICFIL_DC_CHX_SHIFT(ch) ((ch) << 1)
#define MICFIL_DC_CHX(ch) GENMASK((((ch) << 1) + 1), ((ch) << 1))
#define MICFIL_DC_CUTOFF_21HZ 0
#define MICFIL_DC_CUTOFF_83HZ 1
#define MICFIL_DC_CUTOFF_152Hz 2
#define MICFIL_DC_BYPASS 3
/* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/
#define MICFIL_VAD0_CTRL1_CHSEL GENMASK(26, 24)
#define MICFIL_VAD0_CTRL1_CICOSR GENMASK(19, 16)