ARM: dts: imx: e60k02: add second uart
There is another uart next to the console uart used by vendor uboot and kernel, enable it and document its location. Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -278,6 +278,12 @@
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};
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&uart1 {
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/* J4, through-hole */
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status = "okay";
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};
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&uart4 {
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/* TP198, next to J4, SMD pads */
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status = "okay";
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};
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@ -94,7 +94,6 @@
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MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x79
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MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79
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MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x79
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MX6SL_PAD_KEY_ROW6__GPIO4_IO05 0x79
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>;
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};
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@ -160,6 +159,13 @@
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>;
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};
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pinctrl_uart4: uart4grp {
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fsl,pins = <
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MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1b0b1
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MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x1b0b1
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>;
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};
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pinctrl_usbotg1: usbotg1grp {
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fsl,pins = <
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MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
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@ -300,6 +306,11 @@
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pinctrl-0 = <&pinctrl_uart1>;
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};
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart4>;
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};
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
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pinctrl-0 = <&pinctrl_usdhc2>;
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@ -104,7 +104,6 @@
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MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x79
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MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79
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MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x79
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MX6SLL_PAD_KEY_ROW6__GPIO4_IO05 0x79
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>;
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};
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@ -170,6 +169,13 @@
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>;
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};
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pinctrl_uart4: uart4grp {
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fsl,pins = <
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MX6SLL_PAD_KEY_ROW6__UART4_DCE_TX 0x1b0b1
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MX6SLL_PAD_KEY_COL6__UART4_DCE_RX 0x1b0b1
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>;
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};
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pinctrl_usbotg1: usbotg1grp {
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fsl,pins = <
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MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
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@ -302,6 +308,11 @@
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pinctrl-0 = <&pinctrl_uart1>;
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};
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart4>;
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};
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep";
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pinctrl-0 = <&pinctrl_usdhc2>;
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