drm/armada: use old_state for update tracking in atomic_update()
Rather than tracking the register state, we can now check the previous state and decide which registers need updating from that since the old plane state indicates the previous state which was programmed into the hardware. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
This commit is contained in:
Russell King
parent
9c41467c9a
commit
3acea7b9b6
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@ -1114,64 +1114,14 @@ int armada_drm_plane_atomic_check(struct drm_plane *plane,
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return 0;
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}
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static unsigned int armada_drm_primary_update_state(
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struct drm_plane_state *state, struct armada_regs *regs)
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{
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struct armada_plane *dplane = drm_to_armada_plane(state->plane);
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struct armada_crtc *dcrtc = drm_to_armada_crtc(state->crtc);
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struct armada_framebuffer *dfb = drm_fb_to_armada_fb(state->fb);
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bool was_disabled;
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unsigned int idx = 0;
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u32 val;
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val = CFG_GRA_FMT(dfb->fmt) | CFG_GRA_MOD(dfb->mod);
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if (dfb->fmt > CFG_420)
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val |= CFG_PALETTE_ENA;
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if (state->visible)
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val |= CFG_GRA_ENA;
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if (drm_rect_width(&state->src) >> 16 != drm_rect_width(&state->dst))
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val |= CFG_GRA_HSMOOTH;
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if (dcrtc->interlaced)
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val |= CFG_GRA_FTOGGLE;
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was_disabled = !(dplane->state.ctrl0 & CFG_GRA_ENA);
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if (was_disabled)
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armada_reg_queue_mod(regs, idx,
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0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1);
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dplane->state.ctrl0 = val;
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dplane->state.src_hw = armada_rect_hw_fp(&state->src);
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dplane->state.dst_hw = armada_rect_hw(&state->dst);
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dplane->state.dst_yx = armada_rect_yx(&state->dst);
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idx += armada_drm_crtc_calc_fb(&dfb->fb, state->src.x1 >> 16,
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state->src.y1 >> 16, regs + idx,
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dcrtc->interlaced);
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armada_reg_queue_set(regs, idx, dplane->state.dst_yx,
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LCD_SPU_GRA_OVSA_HPXL_VLN);
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armada_reg_queue_set(regs, idx, dplane->state.src_hw,
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LCD_SPU_GRA_HPXL_VLN);
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armada_reg_queue_set(regs, idx, dplane->state.dst_hw,
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LCD_SPU_GZM_HPXL_VLN);
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armada_reg_queue_mod(regs, idx, dplane->state.ctrl0, CFG_GRAFORMAT |
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CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
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CFG_SWAPYU | CFG_YUV2RGB) |
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CFG_PALETTE_ENA | CFG_GRA_FTOGGLE |
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CFG_GRA_HSMOOTH | CFG_GRA_ENA,
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LCD_SPU_DMA_CTRL0);
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dplane->state.vsync_update = !was_disabled;
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dplane->state.changed = true;
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return idx;
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}
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static void armada_drm_primary_plane_atomic_update(struct drm_plane *plane,
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struct drm_plane_state *old_state)
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{
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struct drm_plane_state *state = plane->state;
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struct armada_crtc *dcrtc;
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struct armada_regs *regs;
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u32 cfg, cfg_mask, val;
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unsigned int idx;
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DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name);
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@ -1187,13 +1137,69 @@ static void armada_drm_primary_plane_atomic_update(struct drm_plane *plane,
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dcrtc = drm_to_armada_crtc(state->crtc);
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regs = dcrtc->regs + dcrtc->regs_idx;
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dcrtc->regs_idx += armada_drm_primary_update_state(state, regs);
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idx = 0;
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if (!old_state->visible && state->visible) {
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val = CFG_PDWN64x66;
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if (drm_fb_to_armada_fb(state->fb)->fmt > CFG_420)
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val |= CFG_PDWN256x24;
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armada_reg_queue_mod(regs, idx, 0, val, LCD_SPU_SRAM_PARA1);
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}
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val = armada_rect_hw_fp(&state->src);
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if (armada_rect_hw_fp(&old_state->src) != val)
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armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_HPXL_VLN);
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val = armada_rect_yx(&state->dst);
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if (armada_rect_yx(&old_state->dst) != val)
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armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_OVSA_HPXL_VLN);
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val = armada_rect_hw(&state->dst);
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if (armada_rect_hw(&old_state->dst) != val)
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armada_reg_queue_set(regs, idx, val, LCD_SPU_GZM_HPXL_VLN);
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if (old_state->src.x1 != state->src.x1 ||
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old_state->src.y1 != state->src.y1 ||
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old_state->fb != state->fb) {
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idx += armada_drm_crtc_calc_fb(state->fb,
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state->src.x1 >> 16,
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state->src.y1 >> 16,
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regs + idx,
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dcrtc->interlaced);
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}
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if (old_state->fb != state->fb) {
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cfg = CFG_GRA_FMT(drm_fb_to_armada_fb(state->fb)->fmt) |
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CFG_GRA_MOD(drm_fb_to_armada_fb(state->fb)->mod);
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if (drm_fb_to_armada_fb(state->fb)->fmt > CFG_420)
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cfg |= CFG_PALETTE_ENA;
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if (state->visible)
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cfg |= CFG_GRA_ENA;
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if (dcrtc->interlaced)
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cfg |= CFG_GRA_FTOGGLE;
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cfg_mask = CFG_GRAFORMAT |
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CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
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CFG_SWAPYU | CFG_YUV2RGB) |
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CFG_PALETTE_ENA | CFG_GRA_FTOGGLE |
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CFG_GRA_ENA;
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} else if (old_state->visible != state->visible) {
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cfg = state->visible ? CFG_GRA_ENA : 0;
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cfg_mask = CFG_GRA_ENA;
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} else {
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cfg = cfg_mask = 0;
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}
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if (drm_rect_width(&old_state->src) != drm_rect_width(&state->src) ||
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drm_rect_width(&old_state->dst) != drm_rect_width(&state->dst)) {
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cfg_mask |= CFG_GRA_HSMOOTH;
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if (drm_rect_width(&state->src) >> 16 !=
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drm_rect_width(&state->dst))
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cfg |= CFG_GRA_HSMOOTH;
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}
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if (cfg_mask)
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armada_reg_queue_mod(regs, idx, cfg, cfg_mask,
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LCD_SPU_DMA_CTRL0);
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dcrtc->regs_idx += idx;
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}
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static void armada_drm_primary_plane_atomic_disable(struct drm_plane *plane,
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struct drm_plane_state *old_state)
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{
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struct armada_plane *dplane = drm_to_armada_plane(plane);
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struct armada_crtc *dcrtc;
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struct armada_regs *regs;
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unsigned int idx = 0;
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@ -1208,8 +1214,6 @@ static void armada_drm_primary_plane_atomic_disable(struct drm_plane *plane,
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old_state->crtc->base.id, old_state->crtc->name,
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old_state->fb->base.id);
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dplane->state.ctrl0 &= ~CFG_GRA_ENA;
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dcrtc = drm_to_armada_crtc(old_state->crtc);
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regs = dcrtc->regs + dcrtc->regs_idx;
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@ -45,24 +45,12 @@ struct armada_plane_work {
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struct armada_regs regs[14];
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};
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struct armada_plane_state {
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u16 src_x;
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u16 src_y;
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u32 src_hw;
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u32 dst_hw;
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u32 dst_yx;
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u32 ctrl0;
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bool changed;
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bool vsync_update;
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};
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struct armada_plane {
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struct drm_plane base;
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wait_queue_head_t frame_wait;
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bool next_work;
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struct armada_plane_work works[2];
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struct armada_plane_work *work;
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struct armada_plane_state state;
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};
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#define drm_to_armada_plane(p) container_of(p, struct armada_plane, base)
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@ -35,6 +35,7 @@ struct armada_ovl_plane_properties {
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struct armada_ovl_plane {
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struct armada_plane base;
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bool wait_vblank;
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struct armada_ovl_plane_properties prop;
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};
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#define drm_to_armada_ovl_plane(p) \
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@ -80,117 +81,14 @@ static void armada_ovl_plane_work(struct armada_crtc *dcrtc,
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spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
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}
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static unsigned int armada_ovl_plane_update_state(struct drm_plane_state *state,
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struct armada_regs *regs)
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{
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struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(state->plane);
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struct armada_framebuffer *dfb = drm_fb_to_armada_fb(state->fb);
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const struct drm_format_info *format;
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unsigned int idx = 0;
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bool fb_changed;
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u32 val, ctrl0;
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u16 src_x, src_y;
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ctrl0 = CFG_DMA_FMT(dfb->fmt) | CFG_DMA_MOD(dfb->mod) | CFG_CBSH_ENA;
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if (state->visible)
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ctrl0 |= CFG_DMA_ENA;
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if (drm_rect_width(&state->src) >> 16 != drm_rect_width(&state->dst))
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ctrl0 |= CFG_DMA_HSMOOTH;
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/*
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* Shifting a YUV packed format image by one pixel causes the U/V
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* planes to swap. Compensate for it by also toggling the UV swap.
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*/
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format = dfb->fb.format;
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if (format->num_planes == 1 && state->src.x1 >> 16 & (format->hsub - 1))
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ctrl0 ^= CFG_DMA_MOD(CFG_SWAPUV);
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if (~dplane->base.state.ctrl0 & ctrl0 & CFG_DMA_ENA) {
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/* Power up the Y/U/V FIFOs on ENA 0->1 transitions */
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armada_reg_queue_mod(regs, idx,
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0, CFG_PDWN16x66 | CFG_PDWN32x66,
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LCD_SPU_SRAM_PARA1);
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}
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fb_changed = dplane->base.base.fb != &dfb->fb ||
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dplane->base.state.src_x != state->src.x1 >> 16 ||
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dplane->base.state.src_y != state->src.y1 >> 16;
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dplane->base.state.vsync_update = fb_changed;
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/* FIXME: overlay on an interlaced display */
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if (fb_changed) {
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u32 addrs[3];
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dplane->base.state.src_y = src_y = state->src.y1 >> 16;
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dplane->base.state.src_x = src_x = state->src.x1 >> 16;
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armada_drm_plane_calc_addrs(addrs, &dfb->fb, src_x, src_y);
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armada_reg_queue_set(regs, idx, addrs[0],
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LCD_SPU_DMA_START_ADDR_Y0);
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armada_reg_queue_set(regs, idx, addrs[1],
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LCD_SPU_DMA_START_ADDR_U0);
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armada_reg_queue_set(regs, idx, addrs[2],
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LCD_SPU_DMA_START_ADDR_V0);
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armada_reg_queue_set(regs, idx, addrs[0],
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LCD_SPU_DMA_START_ADDR_Y1);
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armada_reg_queue_set(regs, idx, addrs[1],
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LCD_SPU_DMA_START_ADDR_U1);
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armada_reg_queue_set(regs, idx, addrs[2],
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LCD_SPU_DMA_START_ADDR_V1);
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val = dfb->fb.pitches[0] << 16 | dfb->fb.pitches[0];
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armada_reg_queue_set(regs, idx, val,
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LCD_SPU_DMA_PITCH_YC);
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val = dfb->fb.pitches[1] << 16 | dfb->fb.pitches[2];
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armada_reg_queue_set(regs, idx, val,
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LCD_SPU_DMA_PITCH_UV);
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}
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val = armada_rect_hw_fp(&state->src);
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if (dplane->base.state.src_hw != val) {
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dplane->base.state.src_hw = val;
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armada_reg_queue_set(regs, idx, val,
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LCD_SPU_DMA_HPXL_VLN);
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}
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val = armada_rect_hw(&state->dst);
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if (dplane->base.state.dst_hw != val) {
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dplane->base.state.dst_hw = val;
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armada_reg_queue_set(regs, idx, val,
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LCD_SPU_DZM_HPXL_VLN);
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}
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val = armada_rect_yx(&state->dst);
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if (dplane->base.state.dst_yx != val) {
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dplane->base.state.dst_yx = val;
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armada_reg_queue_set(regs, idx, val,
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LCD_SPU_DMA_OVSA_HPXL_VLN);
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}
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if (dplane->base.state.ctrl0 != ctrl0) {
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dplane->base.state.ctrl0 = ctrl0;
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armada_reg_queue_mod(regs, idx, ctrl0,
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CFG_CBSH_ENA | CFG_DMAFORMAT | CFG_DMA_FTOGGLE |
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CFG_DMA_HSMOOTH | CFG_DMA_TSTMODE |
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CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV | CFG_SWAPYU |
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CFG_YUV2RGB) | CFG_DMA_ENA,
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LCD_SPU_DMA_CTRL0);
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dplane->base.state.vsync_update = true;
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}
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dplane->base.state.changed = idx != 0;
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return idx;
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}
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static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane,
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struct drm_plane_state *old_state)
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{
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struct drm_plane_state *state = plane->state;
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struct armada_crtc *dcrtc;
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struct armada_regs *regs;
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unsigned int idx;
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u32 cfg, cfg_mask, val;
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DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name);
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@ -206,13 +104,96 @@ static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane,
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dcrtc = drm_to_armada_crtc(state->crtc);
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regs = dcrtc->regs + dcrtc->regs_idx;
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dcrtc->regs_idx += armada_ovl_plane_update_state(state, regs);
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drm_to_armada_ovl_plane(plane)->wait_vblank = false;
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idx = 0;
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if (!old_state->visible && state->visible)
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armada_reg_queue_mod(regs, idx,
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0, CFG_PDWN16x66 | CFG_PDWN32x66,
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LCD_SPU_SRAM_PARA1);
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val = armada_rect_hw_fp(&state->src);
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if (armada_rect_hw_fp(&old_state->src) != val)
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armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_HPXL_VLN);
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val = armada_rect_yx(&state->dst);
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if (armada_rect_yx(&old_state->dst) != val)
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armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_OVSA_HPXL_VLN);
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val = armada_rect_hw(&state->dst);
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if (armada_rect_hw(&old_state->dst) != val)
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armada_reg_queue_set(regs, idx, val, LCD_SPU_DZM_HPXL_VLN);
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/* FIXME: overlay on an interlaced display */
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if (old_state->src.x1 != state->src.x1 ||
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old_state->src.y1 != state->src.y1 ||
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old_state->fb != state->fb) {
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const struct drm_format_info *format;
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u16 src_x = state->src.x1 >> 16;
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u16 src_y = state->src.y1 >> 16;
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u32 addrs[3];
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armada_drm_plane_calc_addrs(addrs, state->fb, src_x, src_y);
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armada_reg_queue_set(regs, idx, addrs[0],
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LCD_SPU_DMA_START_ADDR_Y0);
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armada_reg_queue_set(regs, idx, addrs[1],
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LCD_SPU_DMA_START_ADDR_U0);
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armada_reg_queue_set(regs, idx, addrs[2],
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LCD_SPU_DMA_START_ADDR_V0);
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armada_reg_queue_set(regs, idx, addrs[0],
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LCD_SPU_DMA_START_ADDR_Y1);
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armada_reg_queue_set(regs, idx, addrs[1],
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LCD_SPU_DMA_START_ADDR_U1);
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armada_reg_queue_set(regs, idx, addrs[2],
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LCD_SPU_DMA_START_ADDR_V1);
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val = state->fb->pitches[0] << 16 | state->fb->pitches[0];
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armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_YC);
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val = state->fb->pitches[1] << 16 | state->fb->pitches[2];
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armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_UV);
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cfg = CFG_DMA_FMT(drm_fb_to_armada_fb(state->fb)->fmt) |
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CFG_DMA_MOD(drm_fb_to_armada_fb(state->fb)->mod) |
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CFG_CBSH_ENA;
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if (state->visible)
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cfg |= CFG_DMA_ENA;
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/*
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* Shifting a YUV packed format image by one pixel causes the
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* U/V planes to swap. Compensate for it by also toggling
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* the UV swap.
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*/
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format = state->fb->format;
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if (format->num_planes == 1 && src_x & (format->hsub - 1))
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cfg ^= CFG_DMA_MOD(CFG_SWAPUV);
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cfg_mask = CFG_CBSH_ENA | CFG_DMAFORMAT |
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CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV |
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CFG_SWAPYU | CFG_YUV2RGB) |
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CFG_DMA_FTOGGLE | CFG_DMA_TSTMODE |
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CFG_DMA_ENA;
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drm_to_armada_ovl_plane(plane)->wait_vblank = true;
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} else if (old_state->visible != state->visible) {
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cfg = state->visible ? CFG_DMA_ENA : 0;
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cfg_mask = CFG_DMA_ENA;
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} else {
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cfg = cfg_mask = 0;
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}
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if (drm_rect_width(&old_state->src) != drm_rect_width(&state->src) ||
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||||
drm_rect_width(&old_state->dst) != drm_rect_width(&state->dst)) {
|
||||
cfg_mask |= CFG_DMA_HSMOOTH;
|
||||
if (drm_rect_width(&state->src) >> 16 !=
|
||||
drm_rect_width(&state->dst))
|
||||
cfg |= CFG_DMA_HSMOOTH;
|
||||
}
|
||||
|
||||
if (cfg_mask)
|
||||
armada_reg_queue_mod(regs, idx, cfg, cfg_mask,
|
||||
LCD_SPU_DMA_CTRL0);
|
||||
|
||||
dcrtc->regs_idx += idx;
|
||||
}
|
||||
|
||||
static void armada_drm_overlay_plane_atomic_disable(struct drm_plane *plane,
|
||||
struct drm_plane_state *old_state)
|
||||
{
|
||||
struct armada_plane *dplane = drm_to_armada_plane(plane);
|
||||
struct armada_crtc *dcrtc;
|
||||
struct armada_regs *regs;
|
||||
unsigned int idx = 0;
|
||||
|
|
@ -227,8 +208,6 @@ static void armada_drm_overlay_plane_atomic_disable(struct drm_plane *plane,
|
|||
old_state->crtc->base.id, old_state->crtc->name,
|
||||
old_state->fb->base.id);
|
||||
|
||||
dplane->state.ctrl0 &= ~CFG_DMA_ENA;
|
||||
|
||||
dcrtc = drm_to_armada_crtc(old_state->crtc);
|
||||
regs = dcrtc->regs + dcrtc->regs_idx;
|
||||
|
||||
|
|
@ -288,7 +267,7 @@ static int armada_overlay_commit(struct drm_plane *plane,
|
|||
plane_funcs->atomic_update(plane, state);
|
||||
|
||||
/* If nothing was updated, short-circuit */
|
||||
if (!dplane->base.state.changed)
|
||||
if (dcrtc->regs_idx == 0)
|
||||
goto put_state;
|
||||
|
||||
armada_reg_queue_end(dcrtc->regs, dcrtc->regs_idx);
|
||||
|
|
@ -298,7 +277,7 @@ static int armada_overlay_commit(struct drm_plane *plane,
|
|||
armada_drm_plane_work_cancel(dcrtc, &dplane->base);
|
||||
|
||||
/* Just updating the position/size? */
|
||||
if (!dplane->base.state.vsync_update) {
|
||||
if (!dplane->wait_vblank) {
|
||||
armada_ovl_plane_work(dcrtc, work);
|
||||
goto put_state;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue