x86: big ticket locks
This implements ticket lock support for more than 255 CPUs on x86. The code gets switched according to the configured NR_CPUS. Signed-off-by: Nick Piggin <npiggin@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Nick Piggin
Ingo Molnar
parent
938f667198
commit
3a556b26a2
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@ -35,10 +35,35 @@ typedef int _slock_t;
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# define LOCK_PTR_REG "D"
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#endif
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#if (NR_CPUS > 256)
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#error spinlock supports a maximum of 256 CPUs
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#if defined(CONFIG_X86_32) && \
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(defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE))
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/*
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* On PPro SMP or if we are using OOSTORE, we use a locked operation to unlock
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* (PPro errata 66, 92)
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*/
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# define UNLOCK_LOCK_PREFIX LOCK_PREFIX
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#else
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# define UNLOCK_LOCK_PREFIX
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#endif
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/*
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* Ticket locks are conceptually two parts, one indicating the current head of
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* the queue, and the other indicating the current tail. The lock is acquired
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* by atomically noting the tail and incrementing it by one (thus adding
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* ourself to the queue and noting our position), then waiting until the head
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* becomes equal to the the initial value of the tail.
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*
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* We use an xadd covering *both* parts of the lock, to increment the tail and
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* also load the position of the head, which takes care of memory ordering
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* issues and should be optimal for the uncontended case. Note the tail must be
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* in the high part, because a wide xadd increment of the low part would carry
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* up and contaminate the high part.
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*
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* With fewer than 2^8 possible CPUs, we can use x86's partial registers to
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* save some instructions and make the code more elegant. There really isn't
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* much between them in performance though, especially as locks are out of line.
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*/
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#if (NR_CPUS < 256)
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static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
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{
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int tmp = *(volatile signed int *)(&(lock)->slock);
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@ -57,21 +82,6 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
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{
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short inc = 0x0100;
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/*
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* Ticket locks are conceptually two bytes, one indicating the current
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* head of the queue, and the other indicating the current tail. The
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* lock is acquired by atomically noting the tail and incrementing it
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* by one (thus adding ourself to the queue and noting our position),
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* then waiting until the head becomes equal to the the initial value
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* of the tail.
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*
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* This uses a 16-bit xadd to increment the tail and also load the
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* position of the head, which takes care of memory ordering issues
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* and should be optimal for the uncontended case. Note the tail must
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* be in the high byte, otherwise the 16-bit wide increment of the low
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* byte would carry up and contaminate the high byte.
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*/
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__asm__ __volatile__ (
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LOCK_PREFIX "xaddw %w0, %1\n"
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"1:\t"
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@ -111,17 +121,6 @@ static inline int __raw_spin_trylock(raw_spinlock_t *lock)
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return tmp;
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}
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#if defined(CONFIG_X86_32) && \
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(defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE))
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/*
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* On PPro SMP or if we are using OOSTORE, we use a locked operation to unlock
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* (PPro errata 66, 92)
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*/
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# define UNLOCK_LOCK_PREFIX LOCK_PREFIX
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#else
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# define UNLOCK_LOCK_PREFIX
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#endif
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static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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__asm__ __volatile__(
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@ -130,6 +129,77 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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:
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:"memory", "cc");
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}
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#else
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static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
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{
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int tmp = *(volatile signed int *)(&(lock)->slock);
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return (((tmp >> 16) & 0xffff) != (tmp & 0xffff));
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}
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static inline int __raw_spin_is_contended(raw_spinlock_t *lock)
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{
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int tmp = *(volatile signed int *)(&(lock)->slock);
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return (((tmp >> 16) & 0xffff) - (tmp & 0xffff)) > 1;
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}
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static inline void __raw_spin_lock(raw_spinlock_t *lock)
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{
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int inc = 0x00010000;
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int tmp;
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__asm__ __volatile__ (
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"lock ; xaddl %0, %1\n"
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"movzwl %w0, %2\n\t"
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"shrl $16, %0\n\t"
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"1:\t"
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"cmpl %0, %2\n\t"
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"je 2f\n\t"
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"rep ; nop\n\t"
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"movzwl %1, %2\n\t"
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/* don't need lfence here, because loads are in-order */
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"jmp 1b\n"
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"2:"
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:"+Q" (inc), "+m" (lock->slock), "=r" (tmp)
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:
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:"memory", "cc");
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}
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#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
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static inline int __raw_spin_trylock(raw_spinlock_t *lock)
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{
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int tmp;
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int new;
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asm volatile(
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"movl %2,%0\n\t"
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"movl %0,%1\n\t"
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"roll $16, %0\n\t"
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"cmpl %0,%1\n\t"
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"jne 1f\n\t"
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"addl $0x00010000, %1\n\t"
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"lock ; cmpxchgl %1,%2\n\t"
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"1:"
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"sete %b1\n\t"
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"movzbl %b1,%0\n\t"
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:"=&a" (tmp), "=r" (new), "+m" (lock->slock)
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:
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: "memory", "cc");
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return tmp;
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}
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static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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__asm__ __volatile__(
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UNLOCK_LOCK_PREFIX "incw %0"
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:"+m" (lock->slock)
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:
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:"memory", "cc");
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}
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#endif
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static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
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{
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