rtw88: 8821c: add power tracking
The TX power requires to be adjusted based on the thermal value. The actual power will decrease if the thermal value raised, and will increase if the thermal value lowered. Driver comapres the thermal value, as moving averages. If it changes over a limit, driver will modify the TX power index to compensate. Implement rtw_chip_ops::pwr_track() for 8821c. Signed-off-by: Tzu-En Huang <tehuang@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200603094218.19942-3-yhchuang@realtek.com
This commit is contained in:
Tzu-En Huang
Kalle Valo
parent
11fcb119a7
commit
3a4312828c
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@ -1466,6 +1466,7 @@ struct rtw_dm_info {
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u8 thermal_avg[RTW_RF_PATH_MAX];
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u8 thermal_meter_k;
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s8 delta_power_index[RTW_RF_PATH_MAX];
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s8 delta_power_index_last[RTW_RF_PATH_MAX];
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u8 default_ofdm_index;
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bool pwr_trk_triggered;
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bool pwr_trk_init_trigger;
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@ -61,6 +61,46 @@ static int rtw8821c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
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return 0;
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}
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static const u32 rtw8821c_txscale_tbl[] = {
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0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
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0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
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0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
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0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
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};
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static const u8 rtw8821c_get_swing_index(struct rtw_dev *rtwdev)
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{
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u8 i = 0;
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u32 swing, table_value;
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swing = rtw_read32_mask(rtwdev, REG_TXSCALE_A, 0xffe00000);
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for (i = 0; i < ARRAY_SIZE(rtw8821c_txscale_tbl); i++) {
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table_value = rtw8821c_txscale_tbl[i];
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if (swing == table_value)
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break;
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}
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return i;
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}
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static void rtw8821c_pwrtrack_init(struct rtw_dev *rtwdev)
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{
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struct rtw_dm_info *dm_info = &rtwdev->dm_info;
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u8 swing_idx = rtw8821c_get_swing_index(rtwdev);
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if (swing_idx >= ARRAY_SIZE(rtw8821c_txscale_tbl))
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dm_info->default_ofdm_index = 24;
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else
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dm_info->default_ofdm_index = swing_idx;
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ewma_thermal_init(&dm_info->avg_thermal[RF_PATH_A]);
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dm_info->delta_power_index[RF_PATH_A] = 0;
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dm_info->delta_power_index_last[RF_PATH_A] = 0;
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dm_info->pwr_trk_triggered = false;
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dm_info->pwr_trk_init_trigger = true;
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dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
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}
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static void rtw8821c_phy_set_param(struct rtw_dev *rtwdev)
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{
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u8 crystal_cap, val;
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@ -103,6 +143,8 @@ static void rtw8821c_phy_set_param(struct rtw_dev *rtwdev)
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rtw_phy_init(rtwdev);
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rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f;
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rtw8821c_pwrtrack_init(rtwdev);
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}
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static int rtw8821c_mac_init(struct rtw_dev *rtwdev)
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@ -362,6 +404,7 @@ static void rtw8821c_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 channel,
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{
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rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21),
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rtw8821c_get_bb_swing(rtwdev, channel));
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rtw8821c_pwrtrack_init(rtwdev);
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}
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static void rtw8821c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
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@ -597,6 +640,152 @@ static void rtw8821c_phy_calibration(struct rtw_dev *rtwdev)
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rtw8821c_do_iqk(rtwdev);
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}
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static void
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rtw8821c_txagc_swing_offset(struct rtw_dev *rtwdev, u8 pwr_idx_offset,
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s8 pwr_idx_offset_lower,
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s8 *txagc_idx, u8 *swing_idx)
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{
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struct rtw_dm_info *dm_info = &rtwdev->dm_info;
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s8 delta_pwr_idx = dm_info->delta_power_index[RF_PATH_A];
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u8 swing_upper_bound = dm_info->default_ofdm_index + 10;
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u8 swing_lower_bound = 0;
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u8 max_pwr_idx_offset = 0xf;
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s8 agc_index = 0;
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u8 swing_index = dm_info->default_ofdm_index;
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pwr_idx_offset = min_t(u8, pwr_idx_offset, max_pwr_idx_offset);
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pwr_idx_offset_lower = max_t(s8, pwr_idx_offset_lower, -15);
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if (delta_pwr_idx >= 0) {
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if (delta_pwr_idx <= pwr_idx_offset) {
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agc_index = delta_pwr_idx;
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swing_index = dm_info->default_ofdm_index;
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} else if (delta_pwr_idx > pwr_idx_offset) {
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agc_index = pwr_idx_offset;
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swing_index = dm_info->default_ofdm_index +
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delta_pwr_idx - pwr_idx_offset;
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swing_index = min_t(u8, swing_index, swing_upper_bound);
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}
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} else if (delta_pwr_idx < 0) {
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if (delta_pwr_idx >= pwr_idx_offset_lower) {
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agc_index = delta_pwr_idx;
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swing_index = dm_info->default_ofdm_index;
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} else if (delta_pwr_idx < pwr_idx_offset_lower) {
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if (dm_info->default_ofdm_index >
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(pwr_idx_offset_lower - delta_pwr_idx))
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swing_index = dm_info->default_ofdm_index +
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delta_pwr_idx - pwr_idx_offset_lower;
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else
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swing_index = swing_lower_bound;
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agc_index = pwr_idx_offset_lower;
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}
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}
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if (swing_index >= ARRAY_SIZE(rtw8821c_txscale_tbl)) {
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rtw_warn(rtwdev, "swing index overflow\n");
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swing_index = ARRAY_SIZE(rtw8821c_txscale_tbl) - 1;
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}
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*txagc_idx = agc_index;
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*swing_idx = swing_index;
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}
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static void rtw8821c_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 pwr_idx_offset,
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s8 pwr_idx_offset_lower)
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{
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s8 txagc_idx;
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u8 swing_idx;
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rtw8821c_txagc_swing_offset(rtwdev, pwr_idx_offset, pwr_idx_offset_lower,
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&txagc_idx, &swing_idx);
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rtw_write32_mask(rtwdev, REG_TXAGCIDX, GENMASK(6, 1), txagc_idx);
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rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21),
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rtw8821c_txscale_tbl[swing_idx]);
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}
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static void rtw8821c_pwrtrack_set(struct rtw_dev *rtwdev)
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{
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struct rtw_dm_info *dm_info = &rtwdev->dm_info;
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u8 pwr_idx_offset, tx_pwr_idx;
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s8 pwr_idx_offset_lower;
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u8 channel = rtwdev->hal.current_channel;
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u8 band_width = rtwdev->hal.current_band_width;
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u8 regd = rtwdev->regd.txpwr_regd;
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u8 tx_rate = dm_info->tx_rate;
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u8 max_pwr_idx = rtwdev->chip->max_power_index;
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tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, RF_PATH_A, tx_rate,
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band_width, channel, regd);
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tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx);
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pwr_idx_offset = max_pwr_idx - tx_pwr_idx;
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pwr_idx_offset_lower = 0 - tx_pwr_idx;
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rtw8821c_pwrtrack_set_pwr(rtwdev, pwr_idx_offset, pwr_idx_offset_lower);
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}
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static void rtw8821c_phy_pwrtrack(struct rtw_dev *rtwdev)
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{
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struct rtw_dm_info *dm_info = &rtwdev->dm_info;
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struct rtw_swing_table swing_table;
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u8 thermal_value, delta;
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rtw_phy_config_swing_table(rtwdev, &swing_table);
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if (rtwdev->efuse.thermal_meter[0] == 0xff)
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return;
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thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00);
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rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A);
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if (dm_info->pwr_trk_init_trigger)
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dm_info->pwr_trk_init_trigger = false;
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else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value,
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RF_PATH_A))
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goto iqk;
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delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A);
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delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1);
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dm_info->delta_power_index[RF_PATH_A] =
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rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, RF_PATH_A,
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RF_PATH_A, delta);
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if (dm_info->delta_power_index[RF_PATH_A] ==
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dm_info->delta_power_index_last[RF_PATH_A])
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goto iqk;
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else
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dm_info->delta_power_index_last[RF_PATH_A] =
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dm_info->delta_power_index[RF_PATH_A];
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rtw8821c_pwrtrack_set(rtwdev);
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iqk:
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if (rtw_phy_pwrtrack_need_iqk(rtwdev))
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rtw8821c_do_iqk(rtwdev);
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}
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static void rtw8821c_pwr_track(struct rtw_dev *rtwdev)
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{
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struct rtw_efuse *efuse = &rtwdev->efuse;
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struct rtw_dm_info *dm_info = &rtwdev->dm_info;
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if (efuse->power_track_type != 0)
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return;
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if (!dm_info->pwr_trk_triggered) {
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rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER,
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GENMASK(17, 16), 0x03);
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dm_info->pwr_trk_triggered = true;
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return;
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}
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rtw8821c_phy_pwrtrack(rtwdev);
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dm_info->pwr_trk_triggered = false;
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}
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static void rtw8821c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl)
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{
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struct rtw_dm_info *dm_info = &rtwdev->dm_info;
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@ -1060,6 +1249,106 @@ static struct rtw_chip_ops rtw8821c_ops = {
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.false_alarm_statistics = rtw8821c_false_alarm_statistics,
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.phy_calibration = rtw8821c_phy_calibration,
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.cck_pd_set = rtw8821c_phy_cck_pd_set,
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.pwr_track = rtw8821c_pwr_track,
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};
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static const u8 rtw8821c_pwrtrk_5gb_n[][RTW_PWR_TRK_TBL_SZ] = {
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{0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10,
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11, 11, 12, 12, 12, 12, 12},
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{0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11,
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11, 12, 12, 12, 12, 12, 12, 12},
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{0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11,
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11, 12, 12, 12, 12, 12, 12},
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};
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static const u8 rtw8821c_pwrtrk_5gb_p[][RTW_PWR_TRK_TBL_SZ] = {
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{0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11,
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12, 12, 12, 12, 12, 12, 12},
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{0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11,
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12, 12, 12, 12, 12, 12, 12, 12},
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{0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11,
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11, 12, 12, 12, 12, 12, 12, 12},
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};
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static const u8 rtw8821c_pwrtrk_5ga_n[][RTW_PWR_TRK_TBL_SZ] = {
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{0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10,
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11, 11, 12, 12, 12, 12, 12},
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{0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11,
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11, 12, 12, 12, 12, 12, 12, 12},
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{0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11,
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11, 12, 12, 12, 12, 12, 12},
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};
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static const u8 rtw8821c_pwrtrk_5ga_p[][RTW_PWR_TRK_TBL_SZ] = {
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{0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11,
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12, 12, 12, 12, 12, 12, 12},
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{0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11,
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12, 12, 12, 12, 12, 12, 12, 12},
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{0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11,
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11, 12, 12, 12, 12, 12, 12, 12},
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};
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static const u8 rtw8821c_pwrtrk_2gb_n[] = {
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0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4,
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4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9
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};
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static const u8 rtw8821c_pwrtrk_2gb_p[] = {
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0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5,
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5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9
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};
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static const u8 rtw8821c_pwrtrk_2ga_n[] = {
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0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4,
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4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9
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};
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static const u8 rtw8821c_pwrtrk_2ga_p[] = {
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0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5,
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5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9
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};
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static const u8 rtw8821c_pwrtrk_2g_cck_b_n[] = {
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0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
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4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9
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};
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static const u8 rtw8821c_pwrtrk_2g_cck_b_p[] = {
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0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5,
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5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9
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};
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static const u8 rtw8821c_pwrtrk_2g_cck_a_n[] = {
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0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
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4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9
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};
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static const u8 rtw8821c_pwrtrk_2g_cck_a_p[] = {
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0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5,
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5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9
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};
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const struct rtw_pwr_track_tbl rtw8821c_rtw_pwr_track_tbl = {
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.pwrtrk_5gb_n[0] = rtw8821c_pwrtrk_5gb_n[0],
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.pwrtrk_5gb_n[1] = rtw8821c_pwrtrk_5gb_n[1],
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.pwrtrk_5gb_n[2] = rtw8821c_pwrtrk_5gb_n[2],
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.pwrtrk_5gb_p[0] = rtw8821c_pwrtrk_5gb_p[0],
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.pwrtrk_5gb_p[1] = rtw8821c_pwrtrk_5gb_p[1],
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.pwrtrk_5gb_p[2] = rtw8821c_pwrtrk_5gb_p[2],
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.pwrtrk_5ga_n[0] = rtw8821c_pwrtrk_5ga_n[0],
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.pwrtrk_5ga_n[1] = rtw8821c_pwrtrk_5ga_n[1],
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.pwrtrk_5ga_n[2] = rtw8821c_pwrtrk_5ga_n[2],
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.pwrtrk_5ga_p[0] = rtw8821c_pwrtrk_5ga_p[0],
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.pwrtrk_5ga_p[1] = rtw8821c_pwrtrk_5ga_p[1],
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.pwrtrk_5ga_p[2] = rtw8821c_pwrtrk_5ga_p[2],
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.pwrtrk_2gb_n = rtw8821c_pwrtrk_2gb_n,
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.pwrtrk_2gb_p = rtw8821c_pwrtrk_2gb_p,
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.pwrtrk_2ga_n = rtw8821c_pwrtrk_2ga_n,
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.pwrtrk_2ga_p = rtw8821c_pwrtrk_2ga_p,
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.pwrtrk_2g_cckb_n = rtw8821c_pwrtrk_2g_cck_b_n,
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.pwrtrk_2g_cckb_p = rtw8821c_pwrtrk_2g_cck_b_p,
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.pwrtrk_2g_ccka_n = rtw8821c_pwrtrk_2g_cck_a_n,
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.pwrtrk_2g_ccka_p = rtw8821c_pwrtrk_2g_cck_a_p,
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||||
};
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||||
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||||
struct rtw_chip_info rtw8821c_hw_spec = {
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||||
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|
@ -1104,6 +1393,8 @@ struct rtw_chip_info rtw8821c_hw_spec = {
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|||
.rfe_defs = rtw8821c_rfe_defs,
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||||
.rfe_defs_size = ARRAY_SIZE(rtw8821c_rfe_defs),
|
||||
.rx_ldpc = false,
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||||
.pwr_track_tbl = &rtw8821c_rtw_pwr_track_tbl,
|
||||
.iqk_threshold = 8,
|
||||
};
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||||
EXPORT_SYMBOL(rtw8821c_hw_spec);
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||||
|
||||
|
|
|
|||
|
|
@ -200,6 +200,7 @@ _rtw_write32s_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data)
|
|||
#define REG_TXSCALE_A 0xc1c
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||||
#define REG_TXDFIR 0xc20
|
||||
#define REG_RXIGI_A 0xc50
|
||||
#define REG_TXAGCIDX 0xc94
|
||||
#define REG_TRSW 0xca0
|
||||
#define REG_RFESEL0 0xcb0
|
||||
#define REG_RFESEL8 0xcb4
|
||||
|
|
|
|||
Loading…
Reference in New Issue