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clk: stm32mp1: add Debug clocks 

RCC manages clock for debug and trace.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
This commit is contained in:
Gabriel Fernandez 2018-03-08 17:54:05 +01:00 committed by Michael Turquette
parent 44cd455a8e
commit 3a43006783
1 changed files with 22 additions and 0 deletions
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22
drivers/clk/clk-stm32mp1.c
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@ -260,6 +260,10 @@ static const char * const mco2_src[] = {
"ck_mpu", "ck_axi", "ck_mcu", "pll4_p", "ck_hse", "ck_hsi"
};
static const char * const ck_trace_src[] = {
"ck_axi"
};
static const struct clk_div_table axi_div_table[] = {
{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
{ 4, 4 }, { 5, 4 }, { 6, 4 }, { 7, 4 },
@ -280,6 +284,12 @@ static const struct clk_div_table apb_div_table[] = {
{ 0 },
};
static const struct clk_div_table ck_trace_div_table[] = {
{ 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
{ 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
{ 0 },
};
#define MAX_MUX_CLK 2
struct stm32_mmux {
@ -1980,6 +1990,18 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
_GATE(RCC_MCO2CFGR, 12, 0),
_MUX(RCC_MCO2CFGR, 0, 3, 0),
_DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)),
/* Debug clocks */
FIXED_FACTOR(NO_ID, "ck_axi_div2", "ck_axi", 0, 1, 2),
GATE(DBG, "ck_apb_dbg", "ck_axi_div2", 0, RCC_DBGCFGR, 8, 0),
GATE(CK_DBG, "ck_sys_dbg", "ck_axi", 0, RCC_DBGCFGR, 8, 0),
COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE,
_GATE(RCC_DBGCFGR, 9, 0),
_NO_MUX,
_DIV(RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table)),
};
struct stm32_clock_match_data {