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arm64: dts: renesas: Add initial DTSI for RZ/G2LC SoC 

The RZ/G2L and RZ/G2LC SoCs are similar and they share the same DEVID.
RZ/G2LC has fewer peripherals compared to RZ/G2L.

SSI (3 channels vs 4 channels)
GbEthernet (1 channel vs 2 channels)
SCIFA (4 channels vs 5 channels)
ADC is only supported in RZ/G2L.

Add the initial DTSI for the RZ/G2LC SoC by reusing the common
r9a07g044.dtsi file with unsupported device nodes deleted in the below
SoC specific dtsi files.

r9a07g044c1.dtsi => RZ/G2LC R9A07G044C1 SoC specific parts
r9a07g044c2.dtsi => RZ/G2LC R9A07G044C2 SoC specific parts

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211216114305.5842-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das 2021-12-16 11:43:04 +00:00 committed by Geert Uytterhoeven
parent 65d2bc885b
commit 3a3c2a48d8
2 changed files with 52 additions and 0 deletions
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32
arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi Normal file
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2LC R9A07G044C1 SoC specific parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r9a07g044.dtsi"
/ {
compatible = "renesas,r9a07g044c1", "renesas,r9a07g044";
cpus {
/delete-node/ cpu-map;
/delete-node/ cpu@100;
};
timer {
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
};
&soc {
/delete-node/ ssi@1004a800;
/delete-node/ serial@1004c800;
/delete-node/ adc@10059000;
/delete-node/ ethernet@11c30000;
};

20
arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi Normal file
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2LC R9A07G044C2 SoC specific parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r9a07g044.dtsi"
/ {
compatible = "renesas,r9a07g044c2", "renesas,r9a07g044";
};
&soc {
/delete-node/ ssi@1004a800;
/delete-node/ serial@1004c800;
/delete-node/ adc@10059000;
/delete-node/ ethernet@11c30000;
};