bnx2x: Removing CL73 code
This code is disabled, so removing it to avoid confusion Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -29,7 +29,6 @@
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#include "bnx2x.h"
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/********************************************************/
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#define SUPPORT_CL73 0 /* Currently no */
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#define ETH_HLEN 14
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#define ETH_OVREHEAD (ETH_HLEN + 8)/* 8 for CRC + VLAN*/
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#define ETH_MIN_PACKET_SIZE 60
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@ -1208,62 +1207,9 @@ static void bnx2x_set_autoneg(struct link_params *params,
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MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
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reg_val);
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/* Enable Clause 73 Aneg */
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if ((vars->line_speed == SPEED_AUTO_NEG) &&
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(SUPPORT_CL73)) {
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/* Enable BAM Station Manager */
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/* CL73 Autoneg Disabled */
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reg_val = 0;
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CL45_WR_OVER_CL22(bp, params->port,
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params->phy_addr,
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MDIO_REG_BANK_CL73_USERB0,
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MDIO_CL73_USERB0_CL73_BAM_CTRL1,
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(MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
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MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
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MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN));
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/* Merge CL73 and CL37 aneg resolution */
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CL45_RD_OVER_CL22(bp, params->port,
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params->phy_addr,
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MDIO_REG_BANK_CL73_USERB0,
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MDIO_CL73_USERB0_CL73_BAM_CTRL3,
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®_val);
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CL45_WR_OVER_CL22(bp, params->port,
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params->phy_addr,
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MDIO_REG_BANK_CL73_USERB0,
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MDIO_CL73_USERB0_CL73_BAM_CTRL3,
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(reg_val |
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MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR));
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/* Set the CL73 AN speed */
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CL45_RD_OVER_CL22(bp, params->port,
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params->phy_addr,
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MDIO_REG_BANK_CL73_IEEEB1,
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MDIO_CL73_IEEEB1_AN_ADV2, ®_val);
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/* In the SerDes we support only the 1G.
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In the XGXS we support the 10G KX4
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but we currently do not support the KR */
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if (vars->phy_flags & PHY_XGXS_FLAG) {
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DP(NETIF_MSG_LINK, "XGXS\n");
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/* 10G KX4 */
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reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
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} else {
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DP(NETIF_MSG_LINK, "SerDes\n");
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/* 1000M KX */
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reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
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}
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CL45_WR_OVER_CL22(bp, params->port,
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params->phy_addr,
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MDIO_REG_BANK_CL73_IEEEB1,
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MDIO_CL73_IEEEB1_AN_ADV2, reg_val);
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/* CL73 Autoneg Enabled */
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reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
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} else {
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/* CL73 Autoneg Disabled */
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reg_val = 0;
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}
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CL45_WR_OVER_CL22(bp, params->port,
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params->phy_addr,
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MDIO_REG_BANK_CL73_IEEEB0,
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@ -1396,44 +1342,25 @@ static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params,
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static void bnx2x_restart_autoneg(struct link_params *params)
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{
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struct bnx2x *bp = params->bp;
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u16 mii_control;
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DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
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if (SUPPORT_CL73) {
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/* enable and restart clause 73 aneg */
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u16 an_ctrl;
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/* Enable and restart BAM/CL37 aneg */
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CL45_RD_OVER_CL22(bp, params->port,
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params->phy_addr,
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MDIO_REG_BANK_CL73_IEEEB0,
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MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
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&an_ctrl);
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CL45_WR_OVER_CL22(bp, params->port,
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params->phy_addr,
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MDIO_REG_BANK_CL73_IEEEB0,
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MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
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(an_ctrl |
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MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
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MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
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} else {
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/* Enable and restart BAM/CL37 aneg */
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u16 mii_control;
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CL45_RD_OVER_CL22(bp, params->port,
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params->phy_addr,
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MDIO_REG_BANK_COMBO_IEEE0,
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MDIO_COMBO_IEEE0_MII_CONTROL,
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&mii_control);
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DP(NETIF_MSG_LINK,
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"bnx2x_restart_autoneg mii_control before = 0x%x\n",
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mii_control);
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CL45_WR_OVER_CL22(bp, params->port,
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params->phy_addr,
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MDIO_REG_BANK_COMBO_IEEE0,
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MDIO_COMBO_IEEE0_MII_CONTROL,
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(mii_control |
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MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
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MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
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}
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CL45_RD_OVER_CL22(bp, params->port,
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params->phy_addr,
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MDIO_REG_BANK_COMBO_IEEE0,
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MDIO_COMBO_IEEE0_MII_CONTROL,
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&mii_control);
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DP(NETIF_MSG_LINK,
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"bnx2x_restart_autoneg mii_control before = 0x%x\n",
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mii_control);
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CL45_WR_OVER_CL22(bp, params->port,
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params->phy_addr,
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MDIO_REG_BANK_COMBO_IEEE0,
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MDIO_COMBO_IEEE0_MII_CONTROL,
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(mii_control |
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MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
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MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
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}
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static void bnx2x_initialize_sgmii_process(struct link_params *params,
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