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ARM: dts: armada-375: Use the node labels 

Use the node label when possible. As a result it flattens the device tree

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This commit is contained in:
Gregory CLEMENT 2016-11-09 23:59:30 +01:00
parent e4a0709da2
commit 3a33467f42
1 changed files with 136 additions and 133 deletions
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103
arch/arm/boot/dts/armada-375-db.dts
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@ -69,15 +69,36 @@
MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
internal-regs {
spi@10600 {
};
};
&pciec {
status = "okay";
};
/*
* The two PCIe units are accessible through
* standard PCIe slots on the board.
*/
&pcie0 {
/* Port 0, Lane 0 */
status = "okay";
};
&pcie1 {
/* Port 1, Lane 0 */
status = "okay";
};
&spi0 {
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
/*
* SPI conflicts with NAND, so we disable it
* here, and select NAND as the enabled device
* by default.
* SPI conflicts with NAND, so we disable it here, and
* select NAND as the enabled device by default.
*/
status = "disabled";
spi-flash@0 {
@ -87,39 +108,39 @@
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
};
};
i2c@11000 {
&i2c0 {
status = "okay";
clock-frequency = <100000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
};
};
i2c@11100 {
&i2c1 {
status = "okay";
clock-frequency = <100000>;
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
};
};
serial@12000 {
&uart0 {
status = "okay";
};
};
pinctrl {
&pinctrl {
sdio_st_pins: sdio-st-pins {
marvell,pins = "mpp44", "mpp45";
marvell,function = "gpio";
};
};
};
sata@a0000 {
&sata {
status = "okay";
nr-ports = <2>;
};
};
nand: nand@d0000 {
&nand {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
@ -142,25 +163,25 @@
label = "Filesystem";
reg = <0x1000000 0x3f000000>;
};
};
};
usb@54000 {
&usb1 {
status = "okay";
};
};
usb3@58000 {
&usb2 {
status = "okay";
};
};
mvsdio@d4000 {
&sdio {
pinctrl-0 = <&sdio_pins &sdio_st_pins>;
pinctrl-names = "default";
status = "okay";
cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
};
};
mdio {
&mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
@ -168,39 +189,21 @@
phy3: ethernet-phy@3 {
reg = <3>;
};
};
};
ethernet@f0000 {
&ethernet {
status = "okay";
};
eth0@c4000 {
&eth0 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
};
eth1@c5000 {
&eth1 {
status = "okay";
phy = <&phy3>;
phy-mode = "gmii";
};
};
};
pcie-controller {
status = "okay";
/*
* The two PCIe units are accessible through
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
};
};