rtlwifi: remove duplicate declarations and macros in headers

This patch brings no functional change.

There are still duplicate macros across the rtlwifi directory, for example
IQK_DELAY_TIME is defined multiple times, sometimes with different values,
this patch only removes duplicates within the same header file.

Signed-off-by: Catalin Iacob <iacobcatalin@gmail.com>
Acked-by: Larry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Catalin Iacob 2013-09-22 11:06:26 +02:00 committed by John W. Linville
parent 551ed40969
commit 3a1ea9fd93
8 changed files with 0 additions and 38 deletions

View File

@ -114,7 +114,6 @@ void rtl_init_rfkill(struct ieee80211_hw *hw);
void rtl_deinit_rfkill(struct ieee80211_hw *hw); void rtl_deinit_rfkill(struct ieee80211_hw *hw);
void rtl_beacon_statistic(struct ieee80211_hw *hw, struct sk_buff *skb); void rtl_beacon_statistic(struct ieee80211_hw *hw, struct sk_buff *skb);
void rtl_watch_dog_timer_callback(unsigned long data);
void rtl_deinit_deferred_work(struct ieee80211_hw *hw); void rtl_deinit_deferred_work(struct ieee80211_hw *hw);
bool rtl_action_proc(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx); bool rtl_action_proc(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx);

View File

@ -39,9 +39,7 @@
#define RT_CANNOT_IO(hw) false #define RT_CANNOT_IO(hw) false
#define HIGHPOWER_RADIOA_ARRAYLEN 22 #define HIGHPOWER_RADIOA_ARRAYLEN 22
#define IQK_ADDA_REG_NUM 16
#define MAX_TOLERANCE 5 #define MAX_TOLERANCE 5
#define IQK_DELAY_TIME 1
#define APK_BB_REG_NUM 5 #define APK_BB_REG_NUM 5
#define APK_AFE_REG_NUM 16 #define APK_AFE_REG_NUM 16

View File

@ -152,8 +152,6 @@ enum version_8192c {
#define IS_VENDOR_UMC_A_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? \ #define IS_VENDOR_UMC_A_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? \
((GET_CVID_CUT_VERSION(version)) ? false : true) : false) ((GET_CVID_CUT_VERSION(version)) ? false : true) : false)
#define IS_CHIP_VER_B(version) ((version & CHIP_VER_B) ? true : false) #define IS_CHIP_VER_B(version) ((version & CHIP_VER_B) ? true : false)
#define IS_VENDOR_UMC_A_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? \
((GET_CVID_CUT_VERSION(version)) ? false : true) : false)
#define IS_92C_SERIAL(version) ((version & CHIP_92C_BITMASK) ? true : false) #define IS_92C_SERIAL(version) ((version & CHIP_92C_BITMASK) ? true : false)
#define IS_CHIP_VENDOR_UMC(version) \ #define IS_CHIP_VENDOR_UMC(version) \
((version & CHIP_VENDOR_UMC) ? true : false) ((version & CHIP_VENDOR_UMC) ? true : false)

View File

@ -39,9 +39,7 @@
#define RT_CANNOT_IO(hw) false #define RT_CANNOT_IO(hw) false
#define HIGHPOWER_RADIOA_ARRAYLEN 22 #define HIGHPOWER_RADIOA_ARRAYLEN 22
#define IQK_ADDA_REG_NUM 16
#define MAX_TOLERANCE 5 #define MAX_TOLERANCE 5
#define IQK_DELAY_TIME 1
#define APK_BB_REG_NUM 5 #define APK_BB_REG_NUM 5
#define APK_AFE_REG_NUM 16 #define APK_AFE_REG_NUM 16
@ -226,7 +224,6 @@ bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
enum radio_path rfpath); enum radio_path rfpath);
bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw, bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw,
u32 rfpath); u32 rfpath);
bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
bool rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw, bool rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
enum rf_pwrstate rfpwr_state); enum rf_pwrstate rfpwr_state);
void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw); void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw);

View File

@ -560,7 +560,6 @@
#define EEPROM_DEFAULT_TXPOWERLEVEL 0x22 #define EEPROM_DEFAULT_TXPOWERLEVEL 0x22
#define EEPROM_DEFAULT_HT40_2SDIFF 0x0 #define EEPROM_DEFAULT_HT40_2SDIFF 0x0
#define EEPROM_DEFAULT_HT20_DIFF 2 #define EEPROM_DEFAULT_HT20_DIFF 2
#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3
#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0 #define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0
#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0 #define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0
@ -639,17 +638,8 @@
#define EEPROM_TXPWR_GROUP 0x6F #define EEPROM_TXPWR_GROUP 0x6F
#define EEPROM_TSSI_A 0x76
#define EEPROM_TSSI_B 0x77
#define EEPROM_THERMAL_METER 0x78
#define EEPROM_CHANNELPLAN 0x75 #define EEPROM_CHANNELPLAN 0x75
#define RF_OPTION1 0x79
#define RF_OPTION2 0x7A
#define RF_OPTION3 0x7B
#define RF_OPTION4 0x7C
#define STOPBECON BIT(6) #define STOPBECON BIT(6)
#define STOPHIGHT BIT(5) #define STOPHIGHT BIT(5)
#define STOPMGT BIT(4) #define STOPMGT BIT(4)
@ -689,13 +679,6 @@
#define RSV_CTRL 0x001C #define RSV_CTRL 0x001C
#define RD_CTRL 0x0524 #define RD_CTRL 0x0524
#define REG_USB_INFO 0xFE17
#define REG_USB_SPECIAL_OPTION 0xFE55
#define REG_USB_DMA_AGG_TO 0xFE5B
#define REG_USB_AGG_TO 0xFE5C
#define REG_USB_AGG_TH 0xFE5D
#define REG_USB_VID 0xFE60 #define REG_USB_VID 0xFE60
#define REG_USB_PID 0xFE62 #define REG_USB_PID 0xFE62
#define REG_USB_OPTIONAL 0xFE64 #define REG_USB_OPTIONAL 0xFE64
@ -1196,9 +1179,6 @@
#define POLLING_LLT_THRESHOLD 20 #define POLLING_LLT_THRESHOLD 20
#define POLLING_READY_TIMEOUT_COUNT 1000 #define POLLING_READY_TIMEOUT_COUNT 1000
#define MAX_MSS_DENSITY_2T 0x13
#define MAX_MSS_DENSITY_1T 0x0A
#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) #define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))
#define EPROM_CMD_CONFIG 0x3 #define EPROM_CMD_CONFIG 0x3
#define EPROM_CMD_LOAD 1 #define EPROM_CMD_LOAD 1

View File

@ -39,9 +39,7 @@
#define RT_CANNOT_IO(hw) false #define RT_CANNOT_IO(hw) false
#define HIGHPOWER_RADIOA_ARRAYLEN 22 #define HIGHPOWER_RADIOA_ARRAYLEN 22
#define IQK_ADDA_REG_NUM 16
#define MAX_TOLERANCE 5 #define MAX_TOLERANCE 5
#define IQK_DELAY_TIME 1
#define APK_BB_REG_NUM 5 #define APK_BB_REG_NUM 5
#define APK_AFE_REG_NUM 16 #define APK_AFE_REG_NUM 16
@ -173,6 +171,5 @@ void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
unsigned long *flag); unsigned long *flag);
u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl); u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl);
void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel); void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel);
void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw);
#endif #endif

View File

@ -425,14 +425,9 @@
#define EXT_IMEM_CODE_DONE BIT(2) #define EXT_IMEM_CODE_DONE BIT(2)
#define IMEM_CHK_RPT BIT(1) #define IMEM_CHK_RPT BIT(1)
#define IMEM_CODE_DONE BIT(0) #define IMEM_CODE_DONE BIT(0)
#define IMEM_CODE_DONE BIT(0)
#define IMEM_CHK_RPT BIT(1)
#define EMEM_CODE_DONE BIT(2) #define EMEM_CODE_DONE BIT(2)
#define EMEM_CHK_RPT BIT(3) #define EMEM_CHK_RPT BIT(3)
#define DMEM_CODE_DONE BIT(4)
#define IMEM_RDY BIT(5) #define IMEM_RDY BIT(5)
#define BASECHG BIT(6)
#define FWRDY BIT(7)
#define LOAD_FW_READY (IMEM_CODE_DONE | \ #define LOAD_FW_READY (IMEM_CODE_DONE | \
IMEM_CHK_RPT | \ IMEM_CHK_RPT | \
EMEM_CODE_DONE | \ EMEM_CODE_DONE | \

View File

@ -192,8 +192,6 @@ enum hardware_type {
(IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal)) (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
#define IS_HARDWARE_TYPE_8723(rtlhal) \ #define IS_HARDWARE_TYPE_8723(rtlhal) \
(IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal)) (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
#define IS_HARDWARE_TYPE_8723U(rtlhal) \
(rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
#define RX_HAL_IS_CCK_RATE(_pdesc)\ #define RX_HAL_IS_CCK_RATE(_pdesc)\
(_pdesc->rxmcs == DESC92_RATE1M || \ (_pdesc->rxmcs == DESC92_RATE1M || \