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[PATCH] ppc32: add dcr_base field to ocp_func_mal_data 

Add dcr_base field to ocp_func_mal_data.  This is preparation step for the
new EMAC driver.

Signed-off-by: Eugene Surovegin <ebs@ebshome.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Eugene Surovegin 2005-09-03 15:55:53 -07:00 committed by Linus Torvalds
parent 28fa031e76
commit 3a0a401b40
9 changed files with 11 additions and 0 deletions
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1
arch/ppc/platforms/4xx/ibm405ep.c
View File

@ -33,6 +33,7 @@ static struct ocp_func_mal_data ibm405ep_mal0_def = {
.txde_irq = 13, /* TX Descriptor Error IRQ */
.rxde_irq = 14, /* RX Descriptor Error IRQ */
.serr_irq = 10, /* MAL System Error IRQ */
.dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
};
OCP_SYSFS_MAL_DATA()

1
arch/ppc/platforms/4xx/ibm405gp.c
View File

@ -46,6 +46,7 @@ static struct ocp_func_mal_data ibm405gp_mal0_def = {
.txde_irq = 13, /* TX Descriptor Error IRQ */
.rxde_irq = 14, /* RX Descriptor Error IRQ */
.serr_irq = 10, /* MAL System Error IRQ */
.dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
};
OCP_SYSFS_MAL_DATA()

1
arch/ppc/platforms/4xx/ibm405gpr.c
View File

@ -42,6 +42,7 @@ static struct ocp_func_mal_data ibm405gpr_mal0_def = {
.txde_irq = 13, /* TX Descriptor Error IRQ */
.rxde_irq = 14, /* RX Descriptor Error IRQ */
.serr_irq = 10, /* MAL System Error IRQ */
.dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
};
OCP_SYSFS_MAL_DATA()

1
arch/ppc/platforms/4xx/ibm440ep.c
View File

@ -53,6 +53,7 @@ static struct ocp_func_mal_data ibm440ep_mal0_def = {
.txde_irq = 33, /* TX Descriptor Error IRQ */
.rxde_irq = 34, /* RX Descriptor Error IRQ */
.serr_irq = 32, /* MAL System Error IRQ */
.dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
};
OCP_SYSFS_MAL_DATA()

1
arch/ppc/platforms/4xx/ibm440gp.c
View File

@ -56,6 +56,7 @@ static struct ocp_func_mal_data ibm440gp_mal0_def = {
.txde_irq = 33, /* TX Descriptor Error IRQ */
.rxde_irq = 34, /* RX Descriptor Error IRQ */
.serr_irq = 32, /* MAL System Error IRQ */
.dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
};
OCP_SYSFS_MAL_DATA()

1
arch/ppc/platforms/4xx/ibm440gx.c
View File

@ -84,6 +84,7 @@ static struct ocp_func_mal_data ibm440gx_mal0_def = {
.txde_irq = 33, /* TX Descriptor Error IRQ */
.rxde_irq = 34, /* RX Descriptor Error IRQ */
.serr_irq = 32, /* MAL System Error IRQ */
.dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
};
OCP_SYSFS_MAL_DATA()

1
arch/ppc/platforms/4xx/ibm440sp.c
View File

@ -43,6 +43,7 @@ static struct ocp_func_mal_data ibm440sp_mal0_def = {
.txde_irq = 34, /* TX Descriptor Error IRQ */
.rxde_irq = 35, /* RX Descriptor Error IRQ */
.serr_irq = 33, /* MAL System Error IRQ */
.dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
};
OCP_SYSFS_MAL_DATA()

1
arch/ppc/platforms/4xx/ibmnp405h.c
View File

@ -73,6 +73,7 @@ static struct ocp_func_mal_data ibmnp405h_mal0_def = {
.txde_irq = 46, /* TX Descriptor Error IRQ */
.rxde_irq = 47, /* RX Descriptor Error IRQ */
.serr_irq = 45, /* MAL System Error IRQ */
.dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
};
OCP_SYSFS_MAL_DATA()

3
include/asm-ppc/ibm_ocp.h
View File

@ -147,6 +147,7 @@ struct ocp_func_mal_data {
int txde_irq; /* TX Descriptor Error IRQ */
int rxde_irq; /* RX Descriptor Error IRQ */
int serr_irq; /* MAL System Error IRQ */
int dcr_base; /* MALx_CFG DCR number */
};
#define OCP_SYSFS_MAL_DATA() \
@ -157,6 +158,7 @@ OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxeob_irq) \
OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txde_irq) \
OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxde_irq) \
OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, serr_irq) \
OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, dcr_base) \
\
void ocp_show_mal_data(struct device *dev) \
{ \
@ -167,6 +169,7 @@ void ocp_show_mal_data(struct device *dev) \
device_create_file(dev, &dev_attr_mal_txde_irq); \
device_create_file(dev, &dev_attr_mal_rxde_irq); \
device_create_file(dev, &dev_attr_mal_serr_irq); \
device_create_file(dev, &dev_attr_mal_dcr_base); \
}
/*