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MIPS: KVM: Add kvm guest support for Loongson-3 

Loongson-3 KVM guest is based on virtio, it use liointc as its interrupt
controller and use GPEX as the pci controller.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Huacai Chen 2020-07-29 14:58:37 +08:00 committed by Thomas Bogendoerfer
parent a84a334f03
commit 39c1485c8b
7 changed files with 125 additions and 3 deletions
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1
arch/mips/Kconfig
View File

@ -478,6 +478,7 @@ config MACH_LOONGSON64
select COMMON_CLK
select USE_OF
select BUILTIN_DTB
select PCI_HOST_GENERIC
help
This enables the support of Loongson-2/3 family of machines.

1
arch/mips/boot/dts/loongson/Makefile
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@ -3,5 +3,6 @@ dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_4core_ls7a.dtb
dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_4core_rs780e.dtb
dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_8core_rs780e.dtb
dtb-$(CONFIG_MACH_LOONGSON64) += loongson64g_4core_ls7a.dtb
dtb-$(CONFIG_MACH_LOONGSON64) += loongson64v_4core_virtio.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

102
arch/mips/boot/dts/loongson/loongson64v_4core_virtio.dts Normal file
View File

@ -0,0 +1,102 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/interrupt-controller/irq.h>
/dts-v1/;
/ {
compatible = "loongson,loongson64v-4core-virtio";
#address-cells = <2>;
#size-cells = <2>;
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
compatible = "mti,cpu-interrupt-controller";
};
package0: bus@1fe00000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
0 0x3ff00000 0 0x3ff00000 0x100000
0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>;
liointc: interrupt-controller@3ff01400 {
compatible = "loongson,liointc-1.0";
reg = <0 0x3ff01400 0x64>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&cpuintc>;
interrupts = <2>, <3>;
interrupt-names = "int0", "int1";
loongson,parent_int_map = <0x00000001>, /* int0 */
<0xfffffffe>, /* int1 */
<0x00000000>, /* int2 */
<0x00000000>; /* int3 */
};
cpu_uart0: serial@1fe001e0 {
compatible = "ns16550a";
reg = <0 0x1fe001e0 0x8>;
clock-frequency = <33000000>;
interrupt-parent = <&liointc>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
no-loopback-test;
};
};
bus@10000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */
0 0x40000000 0 0x40000000 0 0x40000000>; /* PCI MEM */
rtc0: rtc@10081000 {
compatible = "google,goldfish-rtc";
reg = <0 0x10081000 0 0x1000>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&liointc>;
};
pci@1a000000 {
compatible = "pci-host-ecam-generic";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
bus-range = <0x0 0x1f>;
reg = <0 0x1a000000 0 0x02000000>;
ranges = <0x01000000 0x0 0x00004000 0x0 0x18004000 0x0 0x0000c000>,
<0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
interrupt-map = <
0x0000 0x0 0x0 0x1 &liointc 0x2 IRQ_TYPE_LEVEL_HIGH
0x0800 0x0 0x0 0x1 &liointc 0x3 IRQ_TYPE_LEVEL_HIGH
0x1000 0x0 0x0 0x1 &liointc 0x4 IRQ_TYPE_LEVEL_HIGH
0x1800 0x0 0x0 0x1 &liointc 0x5 IRQ_TYPE_LEVEL_HIGH
>;
interrupt-map-mask = <0x1800 0x0 0x0 0x7>;
};
isa {
compatible = "isa";
#address-cells = <2>;
#size-cells = <1>;
ranges = <1 0 0 0x18000000 0x4000>;
};
};
hypervisor {
compatible = "linux,kvm";
};
};

4
arch/mips/include/asm/mach-loongson64/boot_param.h
View File

@ -194,7 +194,8 @@ struct boot_params {
enum loongson_bridge_type {
LS7A = 1,
RS780E = 2
RS780E = 2,
VIRTUAL = 3
};
struct loongson_system_configuration {
@ -230,5 +231,6 @@ extern struct loongson_system_configuration loongson_sysconf;
extern u32 node_id_offset;
extern void ls7a_early_config(void);
extern void rs780e_early_config(void);
extern void virtual_early_config(void);
#endif

1
arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
View File

@ -12,4 +12,5 @@ extern u32 __dtb_loongson64c_4core_ls7a_begin[];
extern u32 __dtb_loongson64c_4core_rs780e_begin[];
extern u32 __dtb_loongson64c_8core_rs780e_begin[];
extern u32 __dtb_loongson64g_4core_ls7a_begin[];
extern u32 __dtb_loongson64v_4core_virtio_begin[];
#endif

14
arch/mips/loongson64/env.c
View File

@ -167,14 +167,24 @@ void __init prom_init_env(void)
vendor = id & 0xffff;
device = (id >> 16) & 0xffff;
if (vendor == PCI_VENDOR_ID_LOONGSON && device == 0x7a00) {
switch (vendor) {
case PCI_VENDOR_ID_LOONGSON:
pr_info("The bridge chip is LS7A\n");
loongson_sysconf.bridgetype = LS7A;
loongson_sysconf.early_config = ls7a_early_config;
} else {
break;
case PCI_VENDOR_ID_AMD:
case PCI_VENDOR_ID_ATI:
pr_info("The bridge chip is RS780E or SR5690\n");
loongson_sysconf.bridgetype = RS780E;
loongson_sysconf.early_config = rs780e_early_config;
break;
default:
pr_info("The bridge chip is VIRTUAL\n");
loongson_sysconf.bridgetype = VIRTUAL;
loongson_sysconf.early_config = virtual_early_config;
loongson_fdt_blob = __dtb_loongson64v_4core_virtio_begin;
break;
}
if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C) {

5
arch/mips/loongson64/init.c
View File

@ -42,6 +42,11 @@ void rs780e_early_config(void)
node_id_offset = 37;
}
void virtual_early_config(void)
{
node_id_offset = 44;
}
void __init prom_init(void)
{
fw_init_cmdline();