Devicetree fixes for 5.4:

Fix a ref count, memory leak, and Risc-V cpu schema warnings.
 -----BEGIN PGP SIGNATURE-----
 
 iQJEBAABCgAuFiEEktVUI4SxYhzZyEuo+vtdtY28YcMFAl2wtukQHHJvYmhAa2Vy
 bmVsLm9yZwAKCRD6+121jbxhwyTdD/4lVzqzzip1CH6yQ4PrNQiSYqMIYhYwnZCJ
 uqaq0OdOQGrLFtM4/YbsU+oeTeV+tBHen5k/C3XtwAowH49TQwPZcgFas43eWVqW
 /FoWqDPwyB94JjgkAsTbpnieHII7ZSKwMGEuCcHPf6ppOZe2Y9VLgsJWG576kwYe
 bZUFJQ7EV+rCaFxWlEYq7kJ1KDPKPIVEqAsULi5TYLRTPPiKUKaYoM525IS+2M0U
 NDn9Szvqoy4+ZC2yBn9bBuG6gdwPp0ZlxhRRY/hyjXYn4keC9x0e1rKpvs1DLE+L
 Uxbb0OZ7mFWyqLdzptSD1WfghxkhjdGhgwYRJccjkPG+iVDHNAsTTdgPsEBSa4x1
 YDnwfkcxkqoYh2tK/TaG7ZGpG5dv7nVhek8IL+bpuvvc9ZdT8mEL6Q86GsKTAEw1
 yBzNrEGryZZV62a3xeaNQKQ8v1b3KJXT110UQyZA0yOT/q7k3QcCJ4tfBB4lNdUS
 9YLig/llunwyJI+vBMu2M3GuiQy0ClsEPemsm1CIvKEZ5uVMiIzhI5MWu5P/KDJ4
 LOYcSYVBtNPhUxMwU0PvIDROJKDTe3g0bVUzarQq+lvsR7muDmmRGvDJT0J6Ziyz
 qqMEqRPYsbJoWiE5PgDQIDBaw1wObZ4mjuBvclffyrUiFX2MHk0O0IydzTwM54I/
 BEm1DnQGbg==
 =vXnQ
 -----END PGP SIGNATURE-----

Merge tag 'devicetree-fixes-for-5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull Devicetree fixes from Rob Herring:
 "A couple more DT fixes for 5.4: fix a ref count, memory leak, and
  Risc-V cpu schema warnings"

* tag 'devicetree-fixes-for-5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
  of: reserved_mem: add missing of_node_put() for proper ref-counting
  of: unittest: fix memory leak in unittest_data_add
  dt-bindings: riscv: Fix CPU schema errors
This commit is contained in:
Linus Torvalds 2019-10-24 18:29:40 -04:00
commit 39a38bcba4
3 changed files with 17 additions and 17 deletions

View File

@ -24,7 +24,8 @@ description: |
properties: properties:
compatible: compatible:
items: oneOf:
- items:
- enum: - enum:
- sifive,rocket0 - sifive,rocket0
- sifive,e5 - sifive,e5
@ -33,6 +34,7 @@ properties:
- sifive,u54 - sifive,u54
- sifive,u5 - sifive,u5
- const: riscv - const: riscv
- const: riscv # Simulator only
description: description:
Identifies that the hart uses the RISC-V instruction set Identifies that the hart uses the RISC-V instruction set
and identifies the type of the hart. and identifies the type of the hart.
@ -66,12 +68,8 @@ properties:
insensitive, letters in the riscv,isa string must be all insensitive, letters in the riscv,isa string must be all
lowercase to simplify parsing. lowercase to simplify parsing.
timebase-frequency: # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
type: integer timebase-frequency: false
minimum: 1
description:
Specifies the clock frequency of the system timer in Hz.
This value is common to all harts on a single system image.
interrupt-controller: interrupt-controller:
type: object type: object
@ -93,7 +91,6 @@ properties:
required: required:
- riscv,isa - riscv,isa
- timebase-frequency
- interrupt-controller - interrupt-controller
examples: examples:

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@ -324,8 +324,10 @@ int of_reserved_mem_device_init_by_idx(struct device *dev,
if (!target) if (!target)
return -ENODEV; return -ENODEV;
if (!of_device_is_available(target)) if (!of_device_is_available(target)) {
of_node_put(target);
return 0; return 0;
}
rmem = __find_rmem(target); rmem = __find_rmem(target);
of_node_put(target); of_node_put(target);

View File

@ -1207,6 +1207,7 @@ static int __init unittest_data_add(void)
of_fdt_unflatten_tree(unittest_data, NULL, &unittest_data_node); of_fdt_unflatten_tree(unittest_data, NULL, &unittest_data_node);
if (!unittest_data_node) { if (!unittest_data_node) {
pr_warn("%s: No tree to attach; not running tests\n", __func__); pr_warn("%s: No tree to attach; not running tests\n", __func__);
kfree(unittest_data);
return -ENODATA; return -ENODATA;
} }