KVM/arm64 fixes for 6.4, take #1
- Plug a race in the stage-2 mapping code where the IPA and the PA would end up being out of sync - Make better use of the bitmap API (bitmap_zero, bitmap_zalloc...) - FP/SVE/SME documentation update, in the hope that this field becomes clearer... - Add workaround for the usual Apple SEIS brokenness - Random comment fixes -----BEGIN PGP SIGNATURE----- iQJDBAABCgAtFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAmRc+84PHG1hekBrZXJu ZWwub3JnAAoJECPQ0LrRPXpD/c8P/jauxMTBh5fqwRuYjgJ31onJEL+S2nnHazLG 9yxdyx3TkPVrIwwg0qkiK5qftTj/UjRWIyTBr+cpfobq/WkzuioZs2pT04jw47/+ WE8IPRb64GJnQV2GvcgEIZgZ/JSVVHtbiPCojppuLbzAiBQ7lvXXKnzCIQOvck0C E7vcYLAX8MXSDU+XYON4uajw8CJpWO3iiyjy4dRlikz2BZ6DRlwKsWGphoyV5jqC 1DsPyGLcPhxi/VS9QHfwEETDAyCLJ11EoHueO/XmW/0W+XZ4wdOkkv1O+LaK287Q x5dbeXT5bVBQ0tjh4QVvlCvQ0KfKBIlR2ystFo44UVAlEGO4XbyxD4U+X5PiLbLb B99ImftDAhPuH85ILEeElZxDy2DJC/3llOWTxIaY+6qUkA5JoCFQBWQG0Y2l2/Um +yycu3FwnOamuYDWd6qHlRKQw0uVvUVhUokh5JUHM4xkLcwY0xknOcPLkrBRiyDP ga9bNbb+ZbwIx8GKrIlKUlKwbwS0ssF705kYDkOnilfwpFdkqApdKYRA2kaImaVQ fa0SSgFsD9g3rbnNpV9TFYCkniczB+CQDofjCAx4nSqmx8iyI686SoIrLZqjSuSH J+0bZFNA0hrrW4y/ukY4b2wAOOiAWMU2CnYo3fTRUJhZF87P/3vwmdN84+by158z un+4a/sw =y6WB -----END PGP SIGNATURE----- Merge tag 'kvmarm-fixes-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD KVM/arm64 fixes for 6.4, take #1 - Plug a race in the stage-2 mapping code where the IPA and the PA would end up being out of sync - Make better use of the bitmap API (bitmap_zero, bitmap_zalloc...) - FP/SVE/SME documentation update, in the hope that this field becomes clearer... - Add workaround for the usual Apple SEIS brokenness - Random comment fixes
This commit is contained in:
Paolo Bonzini
commit
39428f6ea9
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@ -126,6 +126,10 @@
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#define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029
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#define APPLE_CPU_PART_M2_BLIZZARD 0x032
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#define APPLE_CPU_PART_M2_AVALANCHE 0x033
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#define APPLE_CPU_PART_M2_BLIZZARD_PRO 0x034
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#define APPLE_CPU_PART_M2_AVALANCHE_PRO 0x035
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#define APPLE_CPU_PART_M2_BLIZZARD_MAX 0x038
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#define APPLE_CPU_PART_M2_AVALANCHE_MAX 0x039
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#define AMPERE_CPU_PART_AMPERE1 0xAC3
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@ -181,6 +185,10 @@
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#define MIDR_APPLE_M1_FIRESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX)
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#define MIDR_APPLE_M2_BLIZZARD MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD)
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#define MIDR_APPLE_M2_AVALANCHE MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE)
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#define MIDR_APPLE_M2_BLIZZARD_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_PRO)
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#define MIDR_APPLE_M2_AVALANCHE_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_PRO)
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#define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)
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#define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)
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#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
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/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
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@ -209,6 +209,7 @@ struct kvm_pgtable_visit_ctx {
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kvm_pte_t old;
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void *arg;
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struct kvm_pgtable_mm_ops *mm_ops;
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u64 start;
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u64 addr;
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u64 end;
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u32 level;
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@ -81,26 +81,34 @@ void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu)
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fpsimd_kvm_prepare();
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/*
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* We will check TIF_FOREIGN_FPSTATE just before entering the
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* guest in kvm_arch_vcpu_ctxflush_fp() and override this to
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* FP_STATE_FREE if the flag set.
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*/
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vcpu->arch.fp_state = FP_STATE_HOST_OWNED;
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vcpu_clear_flag(vcpu, HOST_SVE_ENABLED);
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if (read_sysreg(cpacr_el1) & CPACR_EL1_ZEN_EL0EN)
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vcpu_set_flag(vcpu, HOST_SVE_ENABLED);
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/*
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* We don't currently support SME guests but if we leave
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* things in streaming mode then when the guest starts running
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* FPSIMD or SVE code it may generate SME traps so as a
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* special case if we are in streaming mode we force the host
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* state to be saved now and exit streaming mode so that we
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* don't have to handle any SME traps for valid guest
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* operations. Do this for ZA as well for now for simplicity.
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*/
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if (system_supports_sme()) {
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vcpu_clear_flag(vcpu, HOST_SME_ENABLED);
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if (read_sysreg(cpacr_el1) & CPACR_EL1_SMEN_EL0EN)
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vcpu_set_flag(vcpu, HOST_SME_ENABLED);
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/*
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* If PSTATE.SM is enabled then save any pending FP
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* state and disable PSTATE.SM. If we leave PSTATE.SM
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* enabled and the guest does not enable SME via
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* CPACR_EL1.SMEN then operations that should be valid
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* may generate SME traps from EL1 to EL1 which we
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* can't intercept and which would confuse the guest.
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*
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* Do the same for PSTATE.ZA in the case where there
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* is state in the registers which has not already
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* been saved, this is very unlikely to happen.
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*/
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if (read_sysreg_s(SYS_SVCR) & (SVCR_SM_MASK | SVCR_ZA_MASK)) {
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vcpu->arch.fp_state = FP_STATE_FREE;
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fpsimd_save_and_flush_cpu_state();
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@ -177,9 +177,17 @@ static bool kvm_hyp_handle_fpsimd(struct kvm_vcpu *vcpu, u64 *exit_code)
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sve_guest = vcpu_has_sve(vcpu);
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esr_ec = kvm_vcpu_trap_get_class(vcpu);
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/* Don't handle SVE traps for non-SVE vcpus here: */
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if (!sve_guest && esr_ec != ESR_ELx_EC_FP_ASIMD)
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/* Only handle traps the vCPU can support here: */
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switch (esr_ec) {
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case ESR_ELx_EC_FP_ASIMD:
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break;
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case ESR_ELx_EC_SVE:
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if (!sve_guest)
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return false;
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break;
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default:
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return false;
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}
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/* Valid trap. Switch the context: */
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@ -58,8 +58,9 @@
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struct kvm_pgtable_walk_data {
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struct kvm_pgtable_walker *walker;
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const u64 start;
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u64 addr;
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u64 end;
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const u64 end;
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};
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static bool kvm_phys_is_valid(u64 phys)
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@ -201,6 +202,7 @@ static inline int __kvm_pgtable_visit(struct kvm_pgtable_walk_data *data,
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.old = READ_ONCE(*ptep),
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.arg = data->walker->arg,
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.mm_ops = mm_ops,
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.start = data->start,
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.addr = data->addr,
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.end = data->end,
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.level = level,
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@ -293,6 +295,7 @@ int kvm_pgtable_walk(struct kvm_pgtable *pgt, u64 addr, u64 size,
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struct kvm_pgtable_walker *walker)
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{
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struct kvm_pgtable_walk_data walk_data = {
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.start = ALIGN_DOWN(addr, PAGE_SIZE),
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.addr = ALIGN_DOWN(addr, PAGE_SIZE),
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.end = PAGE_ALIGN(walk_data.addr + size),
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.walker = walker,
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@ -349,7 +352,7 @@ int kvm_pgtable_get_leaf(struct kvm_pgtable *pgt, u64 addr,
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}
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struct hyp_map_data {
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u64 phys;
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const u64 phys;
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kvm_pte_t attr;
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};
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@ -407,13 +410,12 @@ enum kvm_pgtable_prot kvm_pgtable_hyp_pte_prot(kvm_pte_t pte)
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static bool hyp_map_walker_try_leaf(const struct kvm_pgtable_visit_ctx *ctx,
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struct hyp_map_data *data)
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{
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u64 phys = data->phys + (ctx->addr - ctx->start);
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kvm_pte_t new;
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u64 granule = kvm_granule_size(ctx->level), phys = data->phys;
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if (!kvm_block_mapping_supported(ctx, phys))
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return false;
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data->phys += granule;
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new = kvm_init_valid_leaf_pte(phys, data->attr, ctx->level);
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if (ctx->old == new)
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return true;
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@ -576,7 +578,7 @@ void kvm_pgtable_hyp_destroy(struct kvm_pgtable *pgt)
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}
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struct stage2_map_data {
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u64 phys;
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const u64 phys;
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kvm_pte_t attr;
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u8 owner_id;
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@ -794,20 +796,43 @@ static bool stage2_pte_executable(kvm_pte_t pte)
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return !(pte & KVM_PTE_LEAF_ATTR_HI_S2_XN);
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}
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static u64 stage2_map_walker_phys_addr(const struct kvm_pgtable_visit_ctx *ctx,
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const struct stage2_map_data *data)
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{
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u64 phys = data->phys;
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/*
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* Stage-2 walks to update ownership data are communicated to the map
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* walker using an invalid PA. Avoid offsetting an already invalid PA,
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* which could overflow and make the address valid again.
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*/
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if (!kvm_phys_is_valid(phys))
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return phys;
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/*
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* Otherwise, work out the correct PA based on how far the walk has
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* gotten.
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*/
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return phys + (ctx->addr - ctx->start);
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}
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static bool stage2_leaf_mapping_allowed(const struct kvm_pgtable_visit_ctx *ctx,
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struct stage2_map_data *data)
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{
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u64 phys = stage2_map_walker_phys_addr(ctx, data);
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if (data->force_pte && (ctx->level < (KVM_PGTABLE_MAX_LEVELS - 1)))
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return false;
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return kvm_block_mapping_supported(ctx, data->phys);
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return kvm_block_mapping_supported(ctx, phys);
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}
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static int stage2_map_walker_try_leaf(const struct kvm_pgtable_visit_ctx *ctx,
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struct stage2_map_data *data)
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{
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kvm_pte_t new;
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u64 granule = kvm_granule_size(ctx->level), phys = data->phys;
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u64 phys = stage2_map_walker_phys_addr(ctx, data);
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u64 granule = kvm_granule_size(ctx->level);
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struct kvm_pgtable *pgt = data->mmu->pgt;
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struct kvm_pgtable_mm_ops *mm_ops = ctx->mm_ops;
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@ -841,8 +866,6 @@ static int stage2_map_walker_try_leaf(const struct kvm_pgtable_visit_ctx *ctx,
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stage2_make_pte(ctx, new);
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if (kvm_phys_is_valid(phys))
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data->phys += granule;
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return 0;
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}
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@ -204,7 +204,7 @@ void kvm_inject_size_fault(struct kvm_vcpu *vcpu)
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* Size Fault at level 0, as if exceeding PARange.
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*
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* Non-LPAE guests will only get the external abort, as there
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* is no way to to describe the ASF.
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* is no way to describe the ASF.
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*/
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if (vcpu_el1_is_32bit(vcpu) &&
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!(vcpu_read_sys_reg(vcpu, TCR_EL1) & TTBCR_EAE))
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@ -616,6 +616,10 @@ static const struct midr_range broken_seis[] = {
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MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX),
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MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD),
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MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE),
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MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO),
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MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO),
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MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX),
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MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX),
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{},
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};
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@ -47,7 +47,7 @@ static void flush_context(void)
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int cpu;
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u64 vmid;
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bitmap_clear(vmid_map, 0, NUM_USER_VMIDS);
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bitmap_zero(vmid_map, NUM_USER_VMIDS);
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for_each_possible_cpu(cpu) {
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vmid = atomic64_xchg_relaxed(&per_cpu(active_vmids, cpu), 0);
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@ -182,8 +182,7 @@ int __init kvm_arm_vmid_alloc_init(void)
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*/
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WARN_ON(NUM_USER_VMIDS - 1 <= num_possible_cpus());
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atomic64_set(&vmid_generation, VMID_FIRST_VERSION);
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vmid_map = kcalloc(BITS_TO_LONGS(NUM_USER_VMIDS),
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sizeof(*vmid_map), GFP_KERNEL);
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vmid_map = bitmap_zalloc(NUM_USER_VMIDS, GFP_KERNEL);
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if (!vmid_map)
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return -ENOMEM;
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@ -192,5 +191,5 @@ int __init kvm_arm_vmid_alloc_init(void)
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void __init kvm_arm_vmid_alloc_free(void)
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{
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kfree(vmid_map);
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bitmap_free(vmid_map);
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}
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