mmc: sdhci: Add pre and post reset processing for chip specific reset
Marvell pxa controllers have private registers that may need to be modified before and after a reset is done. For example, the SD reset operation, RESET_ALL, will reset the private registers to their default state. This will cause the clock adjustment registers that may have been programmed to have incorrect values. RESET_DATA sometimes needs to be delayed before the reset is done (depending on SoC) to enable any transactions being handled by the SDIO card to be completed. Needed in pre SD 3.0 silicon to handle clock gating. Implement hooks to allow this to happen. Signed-off-by: Philip Rakity <prakity@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
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@ -156,6 +156,9 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask)
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if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
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if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
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ier = sdhci_readl(host, SDHCI_INT_ENABLE);
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ier = sdhci_readl(host, SDHCI_INT_ENABLE);
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if (host->ops->platform_reset_enter)
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host->ops->platform_reset_enter(host, mask);
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sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
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sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
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if (mask & SDHCI_RESET_ALL)
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if (mask & SDHCI_RESET_ALL)
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@ -176,6 +179,9 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask)
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mdelay(1);
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mdelay(1);
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}
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}
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if (host->ops->platform_reset_exit)
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host->ops->platform_reset_exit(host, mask);
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if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
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if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
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sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
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sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
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}
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}
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@ -229,6 +229,8 @@ struct sdhci_ops {
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void (*platform_send_init_74_clocks)(struct sdhci_host *host,
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void (*platform_send_init_74_clocks)(struct sdhci_host *host,
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u8 power_mode);
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u8 power_mode);
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unsigned int (*get_ro)(struct sdhci_host *host);
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unsigned int (*get_ro)(struct sdhci_host *host);
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void (*platform_reset_enter)(struct sdhci_host *host, u8 mask);
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void (*platform_reset_exit)(struct sdhci_host *host, u8 mask);
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};
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};
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#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
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#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
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