PCI: qcom: Set up rev 2.1.0 PARF_PHY before enabling clocks
We currently enable clocks BEFORE we write to PARF_PHY_CTRL reg to enable
clocks and resets. This causes the driver to never set to a ready state
with the error 'Phy link never came up'.
This is caused by the PHY clock getting enabled before setting the required
bits in the PARF regs.
A workaround for this was set but with this new discovery we can drop
the workaround and use a proper solution to the problem by just enabling
the clock only AFTER the PARF_PHY_CTRL bit is set.
This correctly sets up the PCIe link and makes it usable even when a
bootloader leaves the PCIe link in an undefined state.
Fixes: 82a823833f
("PCI: qcom: Add Qualcomm PCIe controller driver")
Link: https://lore.kernel.org/r/20220708222743.27019-1-ansuelsmth@gmail.com
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
parent
553d12b20c
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38f897ae3d
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@ -337,8 +337,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
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reset_control_assert(res->ext_reset);
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reset_control_assert(res->phy_reset);
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writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL);
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ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
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if (ret < 0) {
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dev_err(dev, "cannot enable regulators\n");
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@ -381,15 +379,15 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
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goto err_deassert_axi;
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}
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ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
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if (ret)
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goto err_clks;
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/* enable PCIe clocks and resets */
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val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
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val &= ~BIT(0);
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writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
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ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
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if (ret)
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goto err_clks;
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if (of_device_is_compatible(node, "qcom,pcie-ipq8064") ||
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of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) {
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writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
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