ARM: cache: add extra feature enable for tauros2
The extra feature may be used by SOCs are prefetch, burst8, write buffer coalesce Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
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@ -8,4 +8,7 @@
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* warranty of any kind, whether express or implied.
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*/
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extern void __init tauros2_init(void);
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#define CACHE_TAUROS2_PREFETCH_ON (1 << 0)
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#define CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1)
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extern void __init tauros2_init(unsigned int features);
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@ -145,21 +145,6 @@ static inline void __init write_extra_features(u32 u)
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__asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u));
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}
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static void __init disable_l2_prefetch(void)
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{
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u32 u;
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/*
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* Read the CPU Extra Features register and verify that the
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* Disable L2 Prefetch bit is set.
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*/
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u = read_extra_features();
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if (!(u & 0x01000000)) {
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printk(KERN_INFO "Tauros2: Disabling L2 prefetch.\n");
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write_extra_features(u | 0x01000000);
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}
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}
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static inline int __init cpuid_scheme(void)
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{
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return !!((processor_id & 0x000f0000) == 0x000f0000);
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@ -188,11 +173,36 @@ static inline void __init write_actlr(u32 actlr)
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__asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr));
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}
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void __init tauros2_init(void)
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static void enable_extra_feature(unsigned int features)
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{
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u32 u;
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u = read_extra_features();
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if (features & CACHE_TAUROS2_PREFETCH_ON)
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u &= ~0x01000000;
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else
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u |= 0x01000000;
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printk(KERN_INFO "Tauros2: %s L2 prefetch.\n",
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(features & CACHE_TAUROS2_PREFETCH_ON)
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? "Enabling" : "Disabling");
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if (features & CACHE_TAUROS2_LINEFILL_BURST8)
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u |= 0x00100000;
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else
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u &= ~0x00100000;
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printk(KERN_INFO "Tauros2: %s line fill burt8.\n",
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(features & CACHE_TAUROS2_LINEFILL_BURST8)
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? "Enabling" : "Disabling");
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write_extra_features(u);
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}
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void __init tauros2_init(unsigned int features)
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{
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char *mode = NULL;
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disable_l2_prefetch();
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enable_extra_feature(features);
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#ifdef CONFIG_CPU_32v5
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if ((processor_id & 0xff0f0000) == 0x56050000) {
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