ahci: qoriq: added a condition to enable dma coherence
Enable DMA coherence in SATA controller on condition that dma-coherent property exists in sata node in DTS. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
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@ -59,6 +59,7 @@ struct ahci_qoriq_priv {
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struct ccsr_ahci *reg_base;
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enum ahci_qoriq_type type;
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void __iomem *ecc_addr;
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bool is_dmacoherent;
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};
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static const struct of_device_id ahci_qoriq_of_match[] = {
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@ -164,26 +165,31 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
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writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
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writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
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writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
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writel(AHCI_PORT_AXICC_CFG, reg_base + LS1021A_AXICC_ADDR);
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if (qpriv->is_dmacoherent)
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writel(AHCI_PORT_AXICC_CFG,
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reg_base + LS1021A_AXICC_ADDR);
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break;
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case AHCI_LS1043A:
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writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
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writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
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writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
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if (qpriv->is_dmacoherent)
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writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
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break;
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case AHCI_LS2080A:
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writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
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writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
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writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
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if (qpriv->is_dmacoherent)
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writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
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break;
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case AHCI_LS1046A:
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writel(LS1046A_SATA_ECC_DIS, qpriv->ecc_addr);
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writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
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writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
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writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
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if (qpriv->is_dmacoherent)
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writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
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break;
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}
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@ -221,6 +227,7 @@ static int ahci_qoriq_probe(struct platform_device *pdev)
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if (IS_ERR(qoriq_priv->ecc_addr))
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return PTR_ERR(qoriq_priv->ecc_addr);
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}
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qoriq_priv->is_dmacoherent = of_dma_is_coherent(np);
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rc = ahci_platform_enable_resources(hpriv);
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if (rc)
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