ath9k_hw: check GPM HW write pointer before chip reset
Both "MAC Warm Reset" and "MCI Reset Rx" will reset GPM HW write_ptr. We should check software cached write_ptr against HW write_ptr before reset. Otherwise the pending DMA data will be lost. Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -893,6 +893,9 @@ void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
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udelay(100);
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}
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/* Check pending GPM msg before MCI Reset Rx */
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ar9003_mci_state(ah, MCI_STATE_CHECK_GPM_OFFSET, NULL);
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regval |= SM(1, AR_MCI_COMMAND2_RESET_RX);
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REG_WRITE(ah, AR_MCI_COMMAND2, regval);
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udelay(1);
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@ -1190,6 +1193,21 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data)
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value = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);
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mci->gpm_idx = value;
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break;
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case MCI_STATE_CHECK_GPM_OFFSET:
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/*
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* This should only be called before "MAC Warm Reset" or
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* "MCI Reset Rx".
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*/
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value = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);
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if (mci->gpm_idx == value)
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break;
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ath_dbg(common, MCI,
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"GPM cached write pointer mismatch %d %d\n",
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mci->gpm_idx, value);
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mci->query_bt = true;
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mci->need_flush_btinfo = true;
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mci->gpm_idx = 0;
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break;
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case MCI_STATE_NEXT_GPM_OFFSET:
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case MCI_STATE_LAST_GPM_OFFSET:
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/*
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@ -190,6 +190,7 @@ enum mci_bt_state {
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enum mci_state_type {
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MCI_STATE_ENABLE,
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MCI_STATE_INIT_GPM_OFFSET,
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MCI_STATE_CHECK_GPM_OFFSET,
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MCI_STATE_NEXT_GPM_OFFSET,
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MCI_STATE_LAST_GPM_OFFSET,
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MCI_STATE_BT,
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@ -1348,6 +1348,9 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
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}
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}
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if (ath9k_hw_mci_is_enabled(ah))
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ar9003_mci_state(ah, MCI_STATE_CHECK_GPM_OFFSET, NULL);
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REG_WRITE(ah, AR_RTC_RC, rst_flags);
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REGWRITE_BUFFER_FLUSH(ah);
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