ARM: dts: qcom: sdx55: Add support for A7 PLL clock

On SDX55 there is a separate A7 PLL which is used to provide high
frequency clock to the Cortex A7 CPU via a MUX.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20210408170457.91409-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Manivannan Sadhasivam 2021-04-08 22:34:43 +05:30 committed by Bjorn Andersson
parent 885aae6860
commit 37f0f245f9
1 changed files with 8 additions and 0 deletions
arch/arm/boot/dts

View File

@ -352,6 +352,14 @@
<0x17802000 0x1000>;
};
a7pll: clock@17808000 {
compatible = "qcom,sdx55-a7pll";
reg = <0x17808000 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "bi_tcxo";
#clock-cells = <0>;
};
watchdog@17817000 {
compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt";
reg = <0x17817000 0x1000>;