ARM: dts: qcom: sdx55: Add support for A7 PLL clock
On SDX55 there is a separate A7 PLL which is used to provide high frequency clock to the Cortex A7 CPU via a MUX. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210408170457.91409-2-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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arch/arm/boot/dts
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@ -352,6 +352,14 @@
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<0x17802000 0x1000>;
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};
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a7pll: clock@17808000 {
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compatible = "qcom,sdx55-a7pll";
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reg = <0x17808000 0x1000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "bi_tcxo";
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#clock-cells = <0>;
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};
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watchdog@17817000 {
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compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt";
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reg = <0x17817000 0x1000>;
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