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drm/i915/icl: update ddb entry start/end mask during hw ddb readout 

Gen11/ICL onward ddb entry start/end mask is increased from 10 bits to
11 bits. This patch make changes to use proper mask for ICL+ during
hardware ddb value readout.

Changes since V1:
 - Use _MASK & _SHIFT macro (James)
Changes since V2:
 - use kernel type u8 instead of uint8_t
Changes since V3:
 - Rebase

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180426142517.16643-4-mahesh1.kumar@intel.com
This commit is contained in:
Mahesh Kumar 2018-04-26 19:55:17 +05:30 committed by Rodrigo Vivi
parent aa9664ffe8
commit 37cde11ba7
2 changed files with 22 additions and 7 deletions
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3
drivers/gpu/drm/i915/i915_reg.h
View File

@ -6504,6 +6504,9 @@ enum {
#define _PLANE_BUF_CFG_1_B 0x7127c
#define _PLANE_BUF_CFG_2_B 0x7137c
#define SKL_DDB_ENTRY_MASK 0x3FF
#define ICL_DDB_ENTRY_MASK 0x7FF
#define DDB_ENTRY_END_SHIFT 16
#define _PLANE_BUF_CFG_1(pipe) \
_PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
#define _PLANE_BUF_CFG_2(pipe) \

26
drivers/gpu/drm/i915/intel_pm.c
View File

@ -3864,10 +3864,18 @@ static unsigned int skl_cursor_allocation(int num_active)
return 8;
}
static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
struct skl_ddb_entry *entry, u32 reg)
{
entry->start = reg & 0x3ff;
entry->end = (reg >> 16) & 0x3ff;
u16 mask;
if (INTEL_GEN(dev_priv) >= 11)
mask = ICL_DDB_ENTRY_MASK;
else
mask = SKL_DDB_ENTRY_MASK;
entry->start = reg & mask;
entry->end = (reg >> DDB_ENTRY_END_SHIFT) & mask;
if (entry->end)
entry->end += 1;
}
@ -3884,7 +3892,8 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
/* Cursor doesn't support NV12/planar, so no extra calculation needed */
if (plane_id == PLANE_CURSOR) {
val = I915_READ(CUR_BUF_CFG(pipe));
skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
skl_ddb_entry_init_from_hw(dev_priv,
&ddb->plane[pipe][plane_id], val);
return;
}
@ -3903,10 +3912,13 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
if (fourcc == DRM_FORMAT_NV12) {
skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val2);
skl_ddb_entry_init_from_hw(&ddb->uv_plane[pipe][plane_id], val);
skl_ddb_entry_init_from_hw(dev_priv,
&ddb->plane[pipe][plane_id], val2);
skl_ddb_entry_init_from_hw(dev_priv,
&ddb->uv_plane[pipe][plane_id], val);
} else {
skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
skl_ddb_entry_init_from_hw(dev_priv,
&ddb->plane[pipe][plane_id], val);
}
}