ath9k_hw: Fix enabling of MCI and RTT
tested in AR9462 Rev:2, both hardware capability flag are set Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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138f07edb6
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3789d59c24
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@ -2390,8 +2390,17 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
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if (AR_SREV_9485_OR_LATER(ah))
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ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
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}
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if (AR_SREV_9462(ah))
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pCap->hw_caps |= ATH9K_HW_CAP_RTT | ATH9K_HW_CAP_MCI;
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if (AR_SREV_9462(ah)) {
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if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
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pCap->hw_caps |= ATH9K_HW_CAP_MCI;
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if (AR_SREV_9462_20(ah))
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pCap->hw_caps |= ATH9K_HW_CAP_RTT;
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}
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return 0;
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}
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@ -1151,6 +1151,7 @@ enum {
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#define AR_INTR_PRIO_ASYNC_ENABLE (AR_SREV_9340(ah) ? 0x4094 : 0x40d4)
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#define AR_ENT_OTP 0x40d8
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#define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000
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#define AR_ENT_OTP_49GHZ_DISABLE 0x00100000
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#define AR_ENT_OTP_MIN_PKT_SIZE_DISABLE 0x00800000
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#define AR_CH0_BB_DPLL1 0x16180
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