MIPS: PCI: remember nasid changed by set interrupt affinity
When changing interrupt affinity remember the possible changed nasid,
otherwise an interrupt deactivate/activate sequence will incorrectly
setup interrupt.
Fixes: e6308b6d35
("MIPS: SGI-IP27: abstract chipset irq from bridge")
Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
Signed-off-by: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
This commit is contained in:
parent
e3d765a941
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37640adbef
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@ -306,16 +306,15 @@ static int bridge_set_affinity(struct irq_data *d, const struct cpumask *mask,
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struct bridge_irq_chip_data *data = d->chip_data;
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struct bridge_irq_chip_data *data = d->chip_data;
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int bit = d->parent_data->hwirq;
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int bit = d->parent_data->hwirq;
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int pin = d->hwirq;
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int pin = d->hwirq;
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nasid_t nasid;
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int ret, cpu;
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int ret, cpu;
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ret = irq_chip_set_affinity_parent(d, mask, force);
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ret = irq_chip_set_affinity_parent(d, mask, force);
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if (ret >= 0) {
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if (ret >= 0) {
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cpu = cpumask_first_and(mask, cpu_online_mask);
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cpu = cpumask_first_and(mask, cpu_online_mask);
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nasid = cpu_to_node(cpu);
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data->nasid = cpu_to_node(cpu);
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bridge_write(data->bc, b_int_addr[pin].addr,
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bridge_write(data->bc, b_int_addr[pin].addr,
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(((data->bc->intr_addr >> 30) & 0x30000) |
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(((data->bc->intr_addr >> 30) & 0x30000) |
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bit | (nasid << 8)));
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bit | (data->nasid << 8)));
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bridge_read(data->bc, b_wid_tflush);
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bridge_read(data->bc, b_wid_tflush);
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}
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}
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return ret;
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return ret;
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