pinctrl: renesas: r8a77970: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 268 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/33dd9bc41df888f132e2e6921d2ff38225b68105.1649865241.git.geert+renesas@glider.be
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34856c5029
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@ -231,7 +231,6 @@
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#define IP8_19_16 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP8_23_20 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP8_27_24 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP8_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define PINMUX_GPSR \
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\
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@ -290,8 +289,7 @@ FM(IP8_11_8) IP8_11_8 \
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FM(IP8_15_12) IP8_15_12 \
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FM(IP8_19_16) IP8_19_16 \
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FM(IP8_23_20) IP8_23_20 \
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FM(IP8_27_24) IP8_27_24 \
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FM(IP8_31_28) IP8_31_28
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FM(IP8_27_24) IP8_27_24
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/* MOD_SEL0 */ /* 0 */ /* 1 */
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#define MOD_SEL0_11 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
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@ -2085,17 +2083,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
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static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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#define F_(x, y) FN_##y
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#define FM(x) FN_##x
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{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
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GROUP(-10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
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GROUP(
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/* GP0_31_22 RESERVED */
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GP_0_21_FN, GPSR0_21,
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GP_0_20_FN, GPSR0_20,
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GP_0_19_FN, GPSR0_19,
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@ -2153,22 +2145,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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GP_1_1_FN, GPSR1_1,
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GP_1_0_FN, GPSR1_0, ))
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},
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{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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{ PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
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GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1),
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GROUP(
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/* GP2_31_17 RESERVED */
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GP_2_16_FN, GPSR2_16,
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GP_2_15_FN, GPSR2_15,
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GP_2_14_FN, GPSR2_14,
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@ -2187,22 +2168,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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GP_2_1_FN, GPSR2_1,
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GP_2_0_FN, GPSR2_0, ))
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},
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{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
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GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1),
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GROUP(
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/* GP3_31_17 RESERVED */
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GP_3_16_FN, GPSR3_16,
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GP_3_15_FN, GPSR3_15,
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GP_3_14_FN, GPSR3_14,
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@ -2221,33 +2191,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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GP_3_1_FN, GPSR3_1,
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GP_3_0_FN, GPSR3_0, ))
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},
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{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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{ PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
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GROUP(-26, 1, 1, 1, 1, 1, 1),
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GROUP(
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/* GP4_31_6 RESERVED */
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GP_4_5_FN, GPSR4_5,
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GP_4_4_FN, GPSR4_4,
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GP_4_3_FN, GPSR4_3,
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@ -2255,24 +2202,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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GP_4_1_FN, GPSR4_1,
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GP_4_0_FN, GPSR4_0, ))
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},
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{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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{ PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
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GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1),
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GROUP(
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/* GP5_31_15 RESERVED */
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GP_5_14_FN, GPSR5_14,
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GP_5_13_FN, GPSR5_13,
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GP_5_12_FN, GPSR5_12,
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@ -2374,8 +2308,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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IP7_7_4
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IP7_3_0 ))
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},
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{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
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IP8_31_28
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{ PINMUX_CFG_REG_VAR("IPSR8", 0xe6060220, 32,
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GROUP(-4, 4, 4, 4, 4, 4, 4, 4),
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GROUP(
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/* IP8_31_28 RESERVED */
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IP8_27_24
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IP8_23_20
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IP8_19_16
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