qed: reformat several structures a bit
Prior to adding new fields and bitfields, reformat the related structures according to the Linux style (spaces to tabs, lowercase hex, indentation etc.). Signed-off-by: Alexander Lobakin <alobakin@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Alexander Lobakin
David S. Miller
parent
3c41486e46
commit
37237b5b71
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@ -11537,7 +11537,7 @@ typedef u32 offsize_t; /* In DWORDS !!! */
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/* PHY configuration */
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struct eth_phy_cfg {
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u32 speed;
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#define ETH_SPEED_AUTONEG 0
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#define ETH_SPEED_AUTONEG 0x0
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#define ETH_SPEED_SMARTLINQ 0x8
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u32 pause;
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@ -11547,23 +11547,24 @@ struct eth_phy_cfg {
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#define ETH_PAUSE_TX 0x4
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u32 adv_speed;
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u32 loopback_mode;
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#define ETH_LOOPBACK_NONE (0)
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#define ETH_LOOPBACK_INT_PHY (1)
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#define ETH_LOOPBACK_EXT_PHY (2)
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#define ETH_LOOPBACK_EXT (3)
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#define ETH_LOOPBACK_MAC (4)
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#define ETH_LOOPBACK_NONE 0x0
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#define ETH_LOOPBACK_INT_PHY 0x1
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#define ETH_LOOPBACK_EXT_PHY 0x2
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#define ETH_LOOPBACK_EXT 0x3
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#define ETH_LOOPBACK_MAC 0x4
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u32 eee_cfg;
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#define EEE_CFG_EEE_ENABLED BIT(0)
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#define EEE_CFG_TX_LPI BIT(1)
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#define EEE_CFG_ADV_SPEED_1G BIT(2)
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#define EEE_CFG_ADV_SPEED_10G BIT(3)
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#define EEE_TX_TIMER_USEC_MASK (0xfffffff0)
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#define EEE_TX_TIMER_USEC_MASK 0xfffffff0
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#define EEE_TX_TIMER_USEC_OFFSET 4
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#define EEE_TX_TIMER_USEC_BALANCED_TIME (0xa00)
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#define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME (0x100)
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#define EEE_TX_TIMER_USEC_LATENCY_TIME (0x6000)
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#define EEE_TX_TIMER_USEC_BALANCED_TIME 0xa00
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#define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME 0x100
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#define EEE_TX_TIMER_USEC_LATENCY_TIME 0x6000
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u32 feature_config_flags;
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#define ETH_EEE_MODE_ADV_LPI (1 << 0)
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@ -11908,12 +11909,9 @@ struct public_port {
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#define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1)
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#define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1)
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#define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1)
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#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
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#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
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#define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
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#define LINK_STATUS_PFC_ENABLED 0x00000100
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#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
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#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
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@ -11923,13 +11921,11 @@ struct public_port {
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#define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000
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#define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000
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#define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000
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#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
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#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000c0000
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#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18)
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#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1 << 18)
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#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18)
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#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18)
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#define LINK_STATUS_SFP_TX_FAULT 0x00100000
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#define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000
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#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000
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@ -12631,23 +12627,23 @@ struct public_drv_mb {
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#define FW_MSG_CODE_MDUMP_INVALID_CMD 0x00030000
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u32 fw_mb_param;
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#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
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#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xffff0000
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#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
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#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
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#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000ffff
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#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
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/* get pf rdma protocol command responce */
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/* Get PF RDMA protocol command response */
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#define FW_MB_PARAM_GET_PF_RDMA_NONE 0x0
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#define FW_MB_PARAM_GET_PF_RDMA_ROCE 0x1
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#define FW_MB_PARAM_GET_PF_RDMA_IWARP 0x2
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#define FW_MB_PARAM_GET_PF_RDMA_BOTH 0x3
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/* get MFW feature support response */
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/* Get MFW feature support response */
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#define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ 0x00000001
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#define FW_MB_PARAM_FEATURE_SUPPORT_EEE 0x00000002
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#define FW_MB_PARAM_FEATURE_SUPPORT_VLINK 0x00010000
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#define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1 << 0)
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#define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR BIT(0)
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#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_MASK 0x00000001
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#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_SHIFT 0
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@ -12658,7 +12654,7 @@ struct public_drv_mb {
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#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_MASK 0x00000008
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#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_SHIFT 3
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#define FW_MB_PARAM_PPFID_BITMAP_MASK 0xFF
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#define FW_MB_PARAM_PPFID_BITMAP_MASK 0xff
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#define FW_MB_PARAM_PPFID_BITMAP_SHIFT 0
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u32 drv_pulse_mb;
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@ -13048,24 +13044,27 @@ struct nvm_cfg1_path {
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};
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struct nvm_cfg1_port {
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u32 reserved__m_relocated_to_option_123;
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u32 reserved__m_relocated_to_option_124;
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u32 rel_to_opt123;
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u32 rel_to_opt124;
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u32 generic_cont0;
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#define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000
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#define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000f0000
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#define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16
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#define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0
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#define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1
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#define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2
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#define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3
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#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000
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#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00f00000
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#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20
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#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1
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#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2
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#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4
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u32 pcie_cfg;
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u32 features;
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u32 speed_cap_mask;
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#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF
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#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000ffff
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#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
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#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1
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#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2
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@ -13074,8 +13073,9 @@ struct nvm_cfg1_port {
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#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
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#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
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#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
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u32 link_settings;
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#define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F
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#define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000f
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#define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0
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#define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0
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#define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1
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@ -13091,12 +13091,13 @@ struct nvm_cfg1_port {
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#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1
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#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2
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#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4
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u32 phy_cfg;
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u32 mgmt_traffic;
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u32 ext_phy;
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/* EEE power saving mode */
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#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00FF0000
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#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00ff0000
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#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET 16
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#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED 0x0
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#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED 0x1
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@ -13110,14 +13111,16 @@ struct nvm_cfg1_port {
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u32 led_port_settings;
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u32 transceiver_00;
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u32 device_ids;
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u32 board_cfg;
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#define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000FF
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#define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000ff
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#define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0
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#define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0
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#define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1
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#define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2
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#define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3
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#define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4
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u32 mnm_10g_cap;
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u32 mnm_10g_ctrl;
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u32 mnm_10g_misc;
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@ -13133,6 +13136,7 @@ struct nvm_cfg1_port {
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u32 mnm_100g_cap;
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u32 mnm_100g_ctrl;
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u32 mnm_100g_misc;
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u32 reserved[116];
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};
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@ -50,7 +50,6 @@ struct qed_mcp_link_capabilities {
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struct qed_mcp_link_state {
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bool link_up;
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u32 min_pf_rate;
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/* Actual link speed in Mb/s */
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@ -60,13 +59,14 @@ struct qed_mcp_link_state {
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* according to PF max bandwidth configuration.
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*/
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u32 speed;
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bool full_duplex;
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bool full_duplex;
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bool an;
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bool an_complete;
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bool parallel_detection;
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bool pfc_enabled;
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u32 partner_adv_speed;
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#define QED_LINK_PARTNER_SPEED_1G_HD BIT(0)
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#define QED_LINK_PARTNER_SPEED_1G_FD BIT(1)
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#define QED_LINK_PARTNER_SPEED_10G BIT(2)
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@ -75,15 +75,14 @@ struct qed_mcp_link_state {
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#define QED_LINK_PARTNER_SPEED_40G BIT(5)
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#define QED_LINK_PARTNER_SPEED_50G BIT(6)
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#define QED_LINK_PARTNER_SPEED_100G BIT(7)
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u32 partner_adv_speed;
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bool partner_tx_flow_ctrl_en;
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bool partner_rx_flow_ctrl_en;
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#define QED_LINK_PARTNER_SYMMETRIC_PAUSE (1)
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#define QED_LINK_PARTNER_ASYMMETRIC_PAUSE (2)
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#define QED_LINK_PARTNER_BOTH_PAUSE (3)
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u8 partner_adv_pause;
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#define QED_LINK_PARTNER_SYMMETRIC_PAUSE 0x1
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#define QED_LINK_PARTNER_ASYMMETRIC_PAUSE 0x2
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#define QED_LINK_PARTNER_BOTH_PAUSE 0x3
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bool sfp_tx_fault;
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bool eee_active;
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@ -664,28 +664,30 @@ enum qed_protocol {
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struct qed_link_params {
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bool link_up;
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u32 override_flags;
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#define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0)
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#define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1)
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#define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2)
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#define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3)
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#define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4)
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#define QED_LINK_OVERRIDE_EEE_CONFIG BIT(5)
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u32 override_flags;
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bool autoneg;
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__ETHTOOL_DECLARE_LINK_MODE_MASK(adv_speeds);
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u32 forced_speed;
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u32 pause_config;
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#define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0)
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#define QED_LINK_PAUSE_RX_ENABLE BIT(1)
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#define QED_LINK_PAUSE_TX_ENABLE BIT(2)
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u32 pause_config;
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u32 loopback_mode;
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#define QED_LINK_LOOPBACK_NONE BIT(0)
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#define QED_LINK_LOOPBACK_INT_PHY BIT(1)
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#define QED_LINK_LOOPBACK_EXT_PHY BIT(2)
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#define QED_LINK_LOOPBACK_EXT BIT(3)
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#define QED_LINK_LOOPBACK_MAC BIT(4)
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u32 loopback_mode;
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struct qed_link_eee_params eee;
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};
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