Merge tag 'drm-intel-fixes-2020-07-01' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes
drm/i915 fixes for v5.8-rc4: - GVT fixes - Include asm sources for render cache clear batches Signed-off-by: Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/87imf7l6ee.fsf@intel.com
This commit is contained in:
commit
370678c5fd
drivers/gpu/drm/i915
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@ -0,0 +1,46 @@
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ASM sources for auto generated shaders
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======================================
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The i915/gt/hsw_clear_kernel.c and i915/gt/ivb_clear_kernel.c files contain
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pre-compiled batch chunks that will clear any residual render cache during
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context switch.
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They are generated from their respective platform ASM files present on
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i915/gt/shaders/clear_kernel directory.
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The generated .c files should never be modified directly. Instead, any modification
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needs to be done on the on their respective ASM files and build instructions below
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needes to be followed.
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Building
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========
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Environment
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-----------
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IGT GPU tool scripts and the Mesa's i965 instruction assembler tool are used
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on building.
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Please make sure your Mesa tool is compiled with "-Dtools=intel" and
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"-Ddri-drivers=i965", and run this script from IGT source root directory"
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The instructions bellow assume:
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* IGT gpu tools source code is located on your home directory (~) as ~/igt
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* Mesa source code is located on your home directory (~) as ~/mesa
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and built under the ~/mesa/build directory
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* Linux kernel source code is under your home directory (~) as ~/linux
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Instructions
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------------
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~ $ cp ~/linux/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm \
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~/igt/lib/i915/shaders/clear_kernel/ivb.asm
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~ $ cd ~/igt
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igt $ ./scripts/generate_clear_kernel.sh -g ivb \
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-m ~/mesa/build/src/intel/tools/i965_asm
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~ $ cp ~/linux/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm \
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~/igt/lib/i915/shaders/clear_kernel/hsw.asm
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~ $ cd ~/igt
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igt $ ./scripts/generate_clear_kernel.sh -g hsw \
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-m ~/mesa/build/src/intel/tools/i965_asm
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@ -0,0 +1,119 @@
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// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2020 Intel Corporation
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*/
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/*
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* Kernel for PAVP buffer clear.
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*
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* 1. Clear all 64 GRF registers assigned to the kernel with designated value;
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* 2. Write 32x16 block of all "0" to render target buffer which indirectly clears
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* 512 bytes of Render Cache.
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*/
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/* Store designated "clear GRF" value */
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mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
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/**
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* Curbe Format
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*
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* DW 1.0 - Block Offset to write Render Cache
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* DW 1.1 [15:0] - Clear Word
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* DW 1.2 - Delay iterations
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* DW 1.3 - Enable Instrumentation (only for debug)
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* DW 1.4 - Rsvd (intended for context ID)
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* DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount
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* DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count)
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* DW 1.7 - Rsvd MBZ (inteded for Total Thread Count)
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*
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* Binding Table
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*
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* BTI 0: 2D Surface to help clear L3 (Render/Data Cache)
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* BTI 1: Wait/Instrumentation Buffer
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* Size : (SliceCount * SubSliceCount * 16 EUs/SubSlice) rows * (16 threads/EU) cols (Format R32_UINT)
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* Expected to be initialized to 0 by driver/another kernel
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* Layout:
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* RowN: Histogram for EU-N: (SliceID*SubSlicePerSliceCount + SSID)*16 + EUID [assume max 16 EUs / SS]
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* Col-k[DW-k]: Threads Executed on ThreadID-k for EU-N
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*/
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add(1) g1.2<1>UD g1.2<0,1,0>UD 0x00000001UD { align1 1N }; /* Loop count to delay kernel: Init to (g1.2 + 1) */
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cmp.z.f0.0(1) null<1>UD g1.3<0,1,0>UD 0x00000000UD { align1 1N };
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(+f0.0) jmpi(1) 352D { align1 WE_all 1N };
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/**
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* State Register has info on where this thread is running
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* IVB: sr0.0 :: [15:13]: MBZ, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
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* HSW: sr0.0 :: 15: MBZ, [14:13]: SliceID, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
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*/
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mov(8) g3<1>UD 0x00000000UD { align1 1Q };
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shr(1) g3<1>D sr0<0,1,0>D 12D { align1 1N };
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and(1) g3<1>D g3<0,1,0>D 1D { align1 1N }; /* g3 has HSID */
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shr(1) g3.1<1>D sr0<0,1,0>D 13D { align1 1N };
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and(1) g3.1<1>D g3.1<0,1,0>D 3D { align1 1N }; /* g3.1 has sliceID */
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mul(1) g3.5<1>D g3.1<0,1,0>D g1.10<0,1,0>UW { align1 1N };
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add(1) g3<1>D g3<0,1,0>D g3.5<0,1,0>D { align1 1N }; /* g3 = sliceID * SubSlicePerSliceCount + HSID */
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shr(1) g3.2<1>D sr0<0,1,0>D 8D { align1 1N };
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and(1) g3.2<1>D g3.2<0,1,0>D 15D { align1 1N }; /* g3.2 = EUID */
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mul(1) g3.4<1>D g3<0,1,0>D 16D { align1 1N };
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add(1) g3.2<1>D g3.2<0,1,0>D g3.4<0,1,0>D { align1 1N }; /* g3.2 now points to EU row number (Y-pixel = V address ) in instrumentation surf */
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mov(8) g5<1>UD 0x00000000UD { align1 1Q };
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and(1) g3.3<1>D sr0<0,1,0>D 7D { align1 1N };
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mul(1) g3.3<1>D g3.3<0,1,0>D 4D { align1 1N };
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mov(8) g4<1>UD g0<8,8,1>UD { align1 1Q }; /* Initialize message header with g0 */
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mov(1) g4<1>UD g3.3<0,1,0>UD { align1 1N }; /* Block offset */
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mov(1) g4.1<1>UD g3.2<0,1,0>UD { align1 1N }; /* Block offset */
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mov(1) g4.2<1>UD 0x00000003UD { align1 1N }; /* Block size (1 row x 4 bytes) */
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and(1) g4.3<1>UD g4.3<0,1,0>UW 0xffffffffUD { align1 1N };
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/* Media block read to fetch current value at specified location in instrumentation buffer */
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sendc(8) g5<1>UD g4<8,8,1>F 0x02190001
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render MsgDesc: media block read MsgCtrl = 0x0 Surface = 1 mlen 1 rlen 1 { align1 1Q };
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add(1) g5<1>D g5<0,1,0>D 1D { align1 1N };
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/* Media block write for updated value at specified location in instrumentation buffer */
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sendc(8) g5<1>UD g4<8,8,1>F 0x040a8001
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render MsgDesc: media block write MsgCtrl = 0x0 Surface = 1 mlen 2 rlen 0 { align1 1Q };
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/* Delay thread for specified parameter */
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add.nz.f0.0(1) g1.2<1>UD g1.2<0,1,0>UD -1D { align1 1N };
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(+f0.0) jmpi(1) -32D { align1 WE_all 1N };
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/* Store designated "clear GRF" value */
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mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
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/* Initialize looping parameters */
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mov(1) a0<1>D 0D { align1 1N }; /* Initialize a0.0:w=0 */
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mov(1) a0.4<1>W 127W { align1 1N }; /* Loop count. Each loop contains 16 GRF's */
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/* Write 32x16 all "0" block */
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mov(8) g2<1>UD g0<8,8,1>UD { align1 1Q };
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mov(8) g127<1>UD g0<8,8,1>UD { align1 1Q };
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mov(2) g2<1>UD g1<2,2,1>UW { align1 1N };
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mov(1) g2.2<1>UD 0x000f000fUD { align1 1N }; /* Block size (16x16) */
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and(1) g2.3<1>UD g2.3<0,1,0>UW 0xffffffefUD { align1 1N };
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mov(16) g3<1>UD 0x00000000UD { align1 1H };
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mov(16) g4<1>UD 0x00000000UD { align1 1H };
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mov(16) g5<1>UD 0x00000000UD { align1 1H };
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mov(16) g6<1>UD 0x00000000UD { align1 1H };
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mov(16) g7<1>UD 0x00000000UD { align1 1H };
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mov(16) g8<1>UD 0x00000000UD { align1 1H };
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mov(16) g9<1>UD 0x00000000UD { align1 1H };
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mov(16) g10<1>UD 0x00000000UD { align1 1H };
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sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
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render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
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add(1) g2<1>UD g1<0,1,0>UW 0x0010UW { align1 1N };
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sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
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render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
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/* Now, clear all GRF registers */
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add.nz.f0.0(1) a0.4<1>W a0.4<0,1,0>W -1W { align1 1N };
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mov(16) g[a0]<1>UW f0.1<0,1,0>UW { align1 1H };
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add(1) a0<1>D a0<0,1,0>D 32D { align1 1N };
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(+f0.0) jmpi(1) -64D { align1 WE_all 1N };
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/* Terminante the thread */
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sendc(8) null<1>UD g127<8,8,1>F 0x82000010
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thread_spawner MsgDesc: mlen 1 rlen 0 { align1 1Q EOT };
|
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@ -0,0 +1,117 @@
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// SPDX-License-Identifier: MIT
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/*
|
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* Copyright © 2020 Intel Corporation
|
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*/
|
||||
|
||||
/*
|
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* Kernel for PAVP buffer clear.
|
||||
*
|
||||
* 1. Clear all 64 GRF registers assigned to the kernel with designated value;
|
||||
* 2. Write 32x16 block of all "0" to render target buffer which indirectly clears
|
||||
* 512 bytes of Render Cache.
|
||||
*/
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|
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/* Store designated "clear GRF" value */
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mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
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/**
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* Curbe Format
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*
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* DW 1.0 - Block Offset to write Render Cache
|
||||
* DW 1.1 [15:0] - Clear Word
|
||||
* DW 1.2 - Delay iterations
|
||||
* DW 1.3 - Enable Instrumentation (only for debug)
|
||||
* DW 1.4 - Rsvd (intended for context ID)
|
||||
* DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount
|
||||
* DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count)
|
||||
* DW 1.7 - Rsvd MBZ (inteded for Total Thread Count)
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||||
*
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||||
* Binding Table
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||||
*
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||||
* BTI 0: 2D Surface to help clear L3 (Render/Data Cache)
|
||||
* BTI 1: Wait/Instrumentation Buffer
|
||||
* Size : (SliceCount * SubSliceCount * 16 EUs/SubSlice) rows * (16 threads/EU) cols (Format R32_UINT)
|
||||
* Expected to be initialized to 0 by driver/another kernel
|
||||
* Layout :
|
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* RowN: Histogram for EU-N: (SliceID*SubSlicePerSliceCount + SSID)*16 + EUID [assume max 16 EUs / SS]
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||||
* Col-k[DW-k]: Threads Executed on ThreadID-k for EU-N
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||||
*/
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add(1) g1.2<1>UD g1.2<0,1,0>UD 0x00000001UD { align1 1N }; /* Loop count to delay kernel: Init to (g1.2 + 1) */
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||||
cmp.z.f0.0(1) null<1>UD g1.3<0,1,0>UD 0x00000000UD { align1 1N };
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||||
(+f0.0) jmpi(1) 44D { align1 WE_all 1N };
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||||
|
||||
/**
|
||||
* State Register has info on where this thread is running
|
||||
* IVB: sr0.0 :: [15:13]: MBZ, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
|
||||
* HSW: sr0.0 :: 15: MBZ, [14:13]: SliceID, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
|
||||
*/
|
||||
mov(8) g3<1>UD 0x00000000UD { align1 1Q };
|
||||
shr(1) g3<1>D sr0<0,1,0>D 12D { align1 1N };
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||||
and(1) g3<1>D g3<0,1,0>D 1D { align1 1N }; /* g3 has HSID */
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||||
shr(1) g3.1<1>D sr0<0,1,0>D 13D { align1 1N };
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||||
and(1) g3.1<1>D g3.1<0,1,0>D 3D { align1 1N }; /* g3.1 has sliceID */
|
||||
mul(1) g3.5<1>D g3.1<0,1,0>D g1.10<0,1,0>UW { align1 1N };
|
||||
add(1) g3<1>D g3<0,1,0>D g3.5<0,1,0>D { align1 1N }; /* g3 = sliceID * SubSlicePerSliceCount + HSID */
|
||||
shr(1) g3.2<1>D sr0<0,1,0>D 8D { align1 1N };
|
||||
and(1) g3.2<1>D g3.2<0,1,0>D 15D { align1 1N }; /* g3.2 = EUID */
|
||||
mul(1) g3.4<1>D g3<0,1,0>D 16D { align1 1N };
|
||||
add(1) g3.2<1>D g3.2<0,1,0>D g3.4<0,1,0>D { align1 1N }; /* g3.2 now points to EU row number (Y-pixel = V address ) in instrumentation surf */
|
||||
|
||||
mov(8) g5<1>UD 0x00000000UD { align1 1Q };
|
||||
and(1) g3.3<1>D sr0<0,1,0>D 7D { align1 1N };
|
||||
mul(1) g3.3<1>D g3.3<0,1,0>D 4D { align1 1N };
|
||||
|
||||
mov(8) g4<1>UD g0<8,8,1>UD { align1 1Q }; /* Initialize message header with g0 */
|
||||
mov(1) g4<1>UD g3.3<0,1,0>UD { align1 1N }; /* Block offset */
|
||||
mov(1) g4.1<1>UD g3.2<0,1,0>UD { align1 1N }; /* Block offset */
|
||||
mov(1) g4.2<1>UD 0x00000003UD { align1 1N }; /* Block size (1 row x 4 bytes) */
|
||||
and(1) g4.3<1>UD g4.3<0,1,0>UW 0xffffffffUD { align1 1N };
|
||||
|
||||
/* Media block read to fetch current value at specified location in instrumentation buffer */
|
||||
sendc(8) g5<1>UD g4<8,8,1>F 0x02190001
|
||||
render MsgDesc: media block read MsgCtrl = 0x0 Surface = 1 mlen 1 rlen 1 { align1 1Q };
|
||||
add(1) g5<1>D g5<0,1,0>D 1D { align1 1N };
|
||||
|
||||
/* Media block write for updated value at specified location in instrumentation buffer */
|
||||
sendc(8) g5<1>UD g4<8,8,1>F 0x040a8001
|
||||
render MsgDesc: media block write MsgCtrl = 0x0 Surface = 1 mlen 2 rlen 0 { align1 1Q };
|
||||
/* Delay thread for specified parameter */
|
||||
add.nz.f0.0(1) g1.2<1>UD g1.2<0,1,0>UD -1D { align1 1N };
|
||||
(+f0.0) jmpi(1) -4D { align1 WE_all 1N };
|
||||
|
||||
/* Store designated "clear GRF" value */
|
||||
mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
|
||||
|
||||
/* Initialize looping parameters */
|
||||
mov(1) a0<1>D 0D { align1 1N }; /* Initialize a0.0:w=0 */
|
||||
mov(1) a0.4<1>W 127W { align1 1N }; /* Loop count. Each loop contains 16 GRF's */
|
||||
|
||||
/* Write 32x16 all "0" block */
|
||||
mov(8) g2<1>UD g0<8,8,1>UD { align1 1Q };
|
||||
mov(8) g127<1>UD g0<8,8,1>UD { align1 1Q };
|
||||
mov(2) g2<1>UD g1<2,2,1>UW { align1 1N };
|
||||
mov(1) g2.2<1>UD 0x000f000fUD { align1 1N }; /* Block size (16x16) */
|
||||
and(1) g2.3<1>UD g2.3<0,1,0>UW 0xffffffefUD { align1 1N };
|
||||
mov(16) g3<1>UD 0x00000000UD { align1 1H };
|
||||
mov(16) g4<1>UD 0x00000000UD { align1 1H };
|
||||
mov(16) g5<1>UD 0x00000000UD { align1 1H };
|
||||
mov(16) g6<1>UD 0x00000000UD { align1 1H };
|
||||
mov(16) g7<1>UD 0x00000000UD { align1 1H };
|
||||
mov(16) g8<1>UD 0x00000000UD { align1 1H };
|
||||
mov(16) g9<1>UD 0x00000000UD { align1 1H };
|
||||
mov(16) g10<1>UD 0x00000000UD { align1 1H };
|
||||
sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
|
||||
render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
|
||||
add(1) g2<1>UD g1<0,1,0>UW 0x0010UW { align1 1N };
|
||||
sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
|
||||
render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
|
||||
|
||||
/* Now, clear all GRF registers */
|
||||
add.nz.f0.0(1) a0.4<1>W a0.4<0,1,0>W -1W { align1 1N };
|
||||
mov(16) g[a0]<1>UW f0.1<0,1,0>UW { align1 1H };
|
||||
add(1) a0<1>D a0<0,1,0>D 32D { align1 1N };
|
||||
(+f0.0) jmpi(1) -8D { align1 WE_all 1N };
|
||||
|
||||
/* Terminante the thread */
|
||||
sendc(8) null<1>UD g127<8,8,1>F 0x82000010
|
||||
thread_spawner MsgDesc: mlen 1 rlen 0 { align1 1Q EOT };
|
|
@ -66,7 +66,7 @@ static inline int mmio_diff_handler(struct intel_gvt *gvt,
|
|||
vreg = vgpu_vreg(param->vgpu, offset);
|
||||
|
||||
if (preg != vreg) {
|
||||
node = kmalloc(sizeof(*node), GFP_KERNEL);
|
||||
node = kmalloc(sizeof(*node), GFP_ATOMIC);
|
||||
if (!node)
|
||||
return -ENOMEM;
|
||||
|
||||
|
|
|
@ -1726,13 +1726,13 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
|
|||
(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2);
|
||||
write_vreg(vgpu, offset, p_data, bytes);
|
||||
|
||||
if (data & _MASKED_BIT_ENABLE(1)) {
|
||||
if (IS_MASKED_BITS_ENABLED(data, 1)) {
|
||||
enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (IS_COFFEELAKE(vgpu->gvt->gt->i915) &&
|
||||
data & _MASKED_BIT_ENABLE(2)) {
|
||||
IS_MASKED_BITS_ENABLED(data, 2)) {
|
||||
enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
|
||||
return 0;
|
||||
}
|
||||
|
@ -1741,14 +1741,14 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
|
|||
* pvinfo, if not, we will treat this guest as non-gvtg-aware
|
||||
* guest, and stop emulating its cfg space, mmio, gtt, etc.
|
||||
*/
|
||||
if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) ||
|
||||
(data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)))
|
||||
&& !vgpu->pv_notified) {
|
||||
if ((IS_MASKED_BITS_ENABLED(data, GFX_PPGTT_ENABLE) ||
|
||||
IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE)) &&
|
||||
!vgpu->pv_notified) {
|
||||
enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
|
||||
return 0;
|
||||
}
|
||||
if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))
|
||||
|| (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) {
|
||||
if (IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE) ||
|
||||
IS_MASKED_BITS_DISABLED(data, GFX_RUN_LIST_ENABLE)) {
|
||||
enable_execlist = !!(data & GFX_RUN_LIST_ENABLE);
|
||||
|
||||
gvt_dbg_core("EXECLIST %s on ring %s\n",
|
||||
|
@ -1809,7 +1809,7 @@ static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
|
|||
write_vreg(vgpu, offset, p_data, bytes);
|
||||
data = vgpu_vreg(vgpu, offset);
|
||||
|
||||
if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET))
|
||||
if (IS_MASKED_BITS_ENABLED(data, RESET_CTL_REQUEST_RESET))
|
||||
data |= RESET_CTL_READY_TO_RESET;
|
||||
else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET))
|
||||
data &= ~RESET_CTL_READY_TO_RESET;
|
||||
|
@ -1827,7 +1827,8 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
|
|||
(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18);
|
||||
write_vreg(vgpu, offset, p_data, bytes);
|
||||
|
||||
if (data & _MASKED_BIT_ENABLE(0x10) || data & _MASKED_BIT_ENABLE(0x8))
|
||||
if (IS_MASKED_BITS_ENABLED(data, 0x10) ||
|
||||
IS_MASKED_BITS_ENABLED(data, 0x8))
|
||||
enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
|
||||
|
||||
return 0;
|
||||
|
@ -3055,6 +3056,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
|
|||
MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
|
||||
MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
|
||||
MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
|
||||
MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
|
||||
|
||||
MMIO_D(CSR_SSP_BASE, D_SKL_PLUS);
|
||||
MMIO_D(CSR_HTP_SKL, D_SKL_PLUS);
|
||||
|
@ -3131,8 +3133,8 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
|
|||
MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
|
||||
NULL, NULL);
|
||||
|
||||
MMIO_D(GAMT_CHKN_BIT_REG, D_KBL);
|
||||
MMIO_D(GEN9_CTX_PREEMPT_REG, D_KBL | D_SKL);
|
||||
MMIO_D(GAMT_CHKN_BIT_REG, D_KBL | D_CFL);
|
||||
MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -54,8 +54,8 @@ bool is_inhibit_context(struct intel_context *ce);
|
|||
|
||||
int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu,
|
||||
struct i915_request *req);
|
||||
#define IS_RESTORE_INHIBIT(a) \
|
||||
(_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) == \
|
||||
((a) & _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT)))
|
||||
|
||||
#define IS_RESTORE_INHIBIT(a) \
|
||||
IS_MASKED_BITS_ENABLED(a, CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT)
|
||||
|
||||
#endif
|
||||
|
|
|
@ -94,6 +94,11 @@
|
|||
#define GFX_MODE_BIT_SET_IN_MASK(val, bit) \
|
||||
((((bit) & 0xffff0000) == 0) && !!((val) & (((bit) << 16))))
|
||||
|
||||
#define IS_MASKED_BITS_ENABLED(_val, _b) \
|
||||
(((_val) & _MASKED_BIT_ENABLE(_b)) == _MASKED_BIT_ENABLE(_b))
|
||||
#define IS_MASKED_BITS_DISABLED(_val, _b) \
|
||||
((_val) & _MASKED_BIT_DISABLE(_b))
|
||||
|
||||
#define FORCEWAKE_RENDER_GEN9_REG 0xa278
|
||||
#define FORCEWAKE_ACK_RENDER_GEN9_REG 0x0D84
|
||||
#define FORCEWAKE_BLITTER_GEN9_REG 0xa188
|
||||
|
|
Loading…
Reference in New Issue