mmc: sdhci-pci-gli: A workaround to allow GL9755 to enter ASPM L1.2
When GL9755 enters ASPM L1 sub-states, it will stay at L1.1 and will not enter L1.2. The workaround is to toggle PM state to allow GL9755 to enter ASPM L1.2. Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20220414094945.457500-1-benchuanggli@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -142,6 +142,9 @@
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#define PCI_GLI_9755_MISC 0x78
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#define PCI_GLI_9755_MISC 0x78
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#define PCI_GLI_9755_MISC_SSC_OFF BIT(26)
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#define PCI_GLI_9755_MISC_SSC_OFF BIT(26)
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#define PCI_GLI_9755_PM_CTRL 0xFC
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#define PCI_GLI_9755_PM_STATE GENMASK(1, 0)
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#define GLI_MAX_TUNING_LOOP 40
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#define GLI_MAX_TUNING_LOOP 40
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/* Genesys Logic chipset */
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/* Genesys Logic chipset */
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@ -676,6 +679,13 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
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GLI_9755_CFG2_L1DLY_VALUE);
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GLI_9755_CFG2_L1DLY_VALUE);
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pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value);
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pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value);
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/* toggle PM state to allow GL9755 to enter ASPM L1.2 */
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pci_read_config_dword(pdev, PCI_GLI_9755_PM_CTRL, &value);
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value |= PCI_GLI_9755_PM_STATE;
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pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
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value &= ~PCI_GLI_9755_PM_STATE;
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pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
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gl9755_wt_off(pdev);
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gl9755_wt_off(pdev);
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}
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}
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