drm/i915: Store power sequencer delays in intel_dp
The power seqeuncer delays are fixed for a given panel, so we can keep them around once computed. Not that on VLV/CHV we still re-compute them every time we initialize the power seqeuncer registers, but that will change soon enough. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä
Daniel Vetter
parent
7a66800e03
commit
36b5f425dd
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@ -283,12 +283,10 @@ intel_hrawclk(struct drm_device *dev)
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static void
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intel_dp_init_panel_power_sequencer(struct drm_device *dev,
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struct intel_dp *intel_dp,
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struct edp_power_seq *out);
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struct intel_dp *intel_dp);
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static void
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intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
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struct intel_dp *intel_dp,
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struct edp_power_seq *out);
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struct intel_dp *intel_dp);
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static void pps_lock(struct intel_dp *intel_dp)
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{
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@ -330,7 +328,6 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_encoder *encoder;
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unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
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struct edp_power_seq power_seq;
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lockdep_assert_held(&dev_priv->pps_mutex);
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@ -368,9 +365,8 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
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port_name(intel_dig_port->port));
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/* init power sequencer on this pipe and port */
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intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
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intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
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&power_seq);
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intel_dp_init_panel_power_sequencer(dev, intel_dp);
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intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
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return intel_dp->pps_pipe;
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}
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@ -425,7 +421,6 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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struct drm_device *dev = intel_dig_port->base.base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct edp_power_seq power_seq;
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enum port port = intel_dig_port->port;
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lockdep_assert_held(&dev_priv->pps_mutex);
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@ -453,9 +448,8 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
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DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
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port_name(port), pipe_name(intel_dp->pps_pipe));
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intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
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intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
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&power_seq);
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intel_dp_init_panel_power_sequencer(dev, intel_dp);
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intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
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}
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void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
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@ -2620,7 +2614,6 @@ static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
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struct drm_device *dev = encoder->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
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struct edp_power_seq power_seq;
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lockdep_assert_held(&dev_priv->pps_mutex);
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@ -2648,9 +2641,8 @@ static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
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pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
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/* init power sequencer on this pipe and port */
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intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
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intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
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&power_seq);
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intel_dp_init_panel_power_sequencer(dev, intel_dp);
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intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
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}
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static void vlv_pre_enable_dp(struct intel_encoder *encoder)
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@ -4731,11 +4723,11 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
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static void
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intel_dp_init_panel_power_sequencer(struct drm_device *dev,
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struct intel_dp *intel_dp,
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struct edp_power_seq *out)
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struct intel_dp *intel_dp)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct edp_power_seq cur, vbt, spec, final;
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struct edp_power_seq cur, vbt, spec,
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*final = &intel_dp->pps_delays;
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u32 pp_on, pp_off, pp_div, pp;
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int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
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@ -4802,7 +4794,7 @@ intel_dp_init_panel_power_sequencer(struct drm_device *dev,
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/* Use the max of the register settings and vbt. If both are
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* unset, fall back to the spec limits. */
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#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
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#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
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spec.field : \
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max(cur.field, vbt.field))
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assign_final(t1_t3);
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@ -4812,7 +4804,7 @@ intel_dp_init_panel_power_sequencer(struct drm_device *dev,
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assign_final(t11_t12);
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#undef assign_final
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#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
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#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
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intel_dp->panel_power_up_delay = get_delay(t1_t3);
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intel_dp->backlight_on_delay = get_delay(t8);
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intel_dp->backlight_off_delay = get_delay(t9);
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@ -4826,21 +4818,18 @@ intel_dp_init_panel_power_sequencer(struct drm_device *dev,
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DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
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intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
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if (out)
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*out = final;
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}
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static void
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intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
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struct intel_dp *intel_dp,
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struct edp_power_seq *seq)
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struct intel_dp *intel_dp)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 pp_on, pp_off, pp_div, port_sel = 0;
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int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
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int pp_on_reg, pp_off_reg, pp_div_reg;
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enum port port = dp_to_dig_port(intel_dp)->port;
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const struct edp_power_seq *seq = &intel_dp->pps_delays;
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lockdep_assert_held(&dev_priv->pps_mutex);
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@ -5058,8 +5047,7 @@ void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
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}
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static bool intel_edp_init_connector(struct intel_dp *intel_dp,
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struct intel_connector *intel_connector,
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struct edp_power_seq *power_seq)
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struct intel_connector *intel_connector)
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{
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struct drm_connector *connector = &intel_connector->base;
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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@ -5095,7 +5083,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
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/* We now know it's not a ghost, init power sequence regs. */
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pps_lock(intel_dp);
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intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
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intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
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pps_unlock(intel_dp);
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mutex_lock(&dev->mode_config.mutex);
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@ -5156,7 +5144,6 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
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struct drm_device *dev = intel_encoder->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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enum port port = intel_dig_port->port;
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struct edp_power_seq power_seq = { 0 };
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int type;
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intel_dp->pps_pipe = INVALID_PIPE;
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@ -5246,8 +5233,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
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vlv_initial_power_sequencer_setup(intel_dp);
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} else {
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intel_dp_init_panel_power_timestamps(intel_dp);
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intel_dp_init_panel_power_sequencer(dev, intel_dp,
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&power_seq);
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intel_dp_init_panel_power_sequencer(dev, intel_dp);
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}
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pps_unlock(intel_dp);
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}
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@ -5262,7 +5248,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
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}
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}
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if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
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if (!intel_edp_init_connector(intel_dp, intel_connector)) {
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drm_dp_aux_unregister(&intel_dp->aux);
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if (is_edp(intel_dp)) {
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cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
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@ -592,6 +592,7 @@ struct intel_dp {
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* this port. Only relevant on VLV/CHV.
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*/
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enum pipe pps_pipe;
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struct edp_power_seq pps_delays;
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bool use_tps3;
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bool can_mst; /* this port supports mst */
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