ASoC: SOF: Intel: pci-mtl: fix ARL-S definitions

[ Upstream commit a00be6dc9bb80796244196033aa5eb258b6af47a ]

The initial copy/paste from MTL was incorrect, the hardware is
different and requires different descriptors along with a dedicated
firmware binary.

Fixes: 3851831f529e ("ASoC: SOF: Intel: pci-mtl: use ARL specific firmware definitions")
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Acked-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20231204212710.185976-5-pierre-louis.bossart@linux.intel.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Stable-dep-of: 1f1b820dc3c6 ("ASoC: SOF: Intel: mtl: Correct rom_status_reg")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Pierre-Louis Bossart 2023-12-04 15:27:09 -06:00 committed by Greg Kroah-Hartman
parent 1ef8f0b414
commit 368017b1bf
3 changed files with 35 additions and 6 deletions

View File

@ -876,6 +876,7 @@ extern const struct sof_intel_dsp_desc ehl_chip_info;
extern const struct sof_intel_dsp_desc jsl_chip_info;
extern const struct sof_intel_dsp_desc adls_chip_info;
extern const struct sof_intel_dsp_desc mtl_chip_info;
extern const struct sof_intel_dsp_desc arl_s_chip_info;
extern const struct sof_intel_dsp_desc lnl_chip_info;
/* Probes support */

View File

@ -743,3 +743,31 @@ const struct sof_intel_dsp_desc mtl_chip_info = {
.hw_ip_version = SOF_INTEL_ACE_1_0,
};
EXPORT_SYMBOL_NS(mtl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
const struct sof_intel_dsp_desc arl_s_chip_info = {
.cores_num = 2,
.init_core_mask = BIT(0),
.host_managed_cores_mask = BIT(0),
.ipc_req = MTL_DSP_REG_HFIPCXIDR,
.ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY,
.ipc_ack = MTL_DSP_REG_HFIPCXIDA,
.ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE,
.ipc_ctl = MTL_DSP_REG_HFIPCXCTL,
.rom_status_reg = MTL_DSP_ROM_STS,
.rom_init_timeout = 300,
.ssp_count = MTL_SSP_COUNT,
.ssp_base_offset = CNL_SSP_BASE_OFFSET,
.sdw_shim_base = SDW_SHIM_BASE_ACE,
.sdw_alh_base = SDW_ALH_BASE_ACE,
.d0i3_offset = MTL_HDA_VS_D0I3C,
.read_sdw_lcount = hda_sdw_check_lcount_common,
.enable_sdw_irq = mtl_enable_sdw_irq,
.check_sdw_irq = mtl_dsp_check_sdw_irq,
.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
.check_ipc_irq = mtl_dsp_check_ipc_irq,
.cl_init = mtl_dsp_cl_init,
.power_down_dsp = mtl_power_down_dsp,
.disable_interrupts = mtl_dsp_disable_interrupts,
.hw_ip_version = SOF_INTEL_ACE_1_0,
};
EXPORT_SYMBOL_NS(arl_s_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);

View File

@ -50,7 +50,7 @@ static const struct sof_dev_desc mtl_desc = {
.ops_free = hda_ops_free,
};
static const struct sof_dev_desc arl_desc = {
static const struct sof_dev_desc arl_s_desc = {
.use_acpi_target_states = true,
.machines = snd_soc_acpi_intel_arl_machines,
.alt_machines = snd_soc_acpi_intel_arl_sdw_machines,
@ -58,21 +58,21 @@ static const struct sof_dev_desc arl_desc = {
.resindex_pcicfg_base = -1,
.resindex_imr_base = -1,
.irqindex_host_ipc = -1,
.chip_info = &mtl_chip_info,
.chip_info = &arl_s_chip_info,
.ipc_supported_mask = BIT(SOF_IPC_TYPE_4),
.ipc_default = SOF_IPC_TYPE_4,
.dspless_mode_supported = true, /* Only supported for HDaudio */
.default_fw_path = {
[SOF_IPC_TYPE_4] = "intel/sof-ipc4/arl",
[SOF_IPC_TYPE_4] = "intel/sof-ipc4/arl-s",
},
.default_lib_path = {
[SOF_IPC_TYPE_4] = "intel/sof-ipc4-lib/arl",
[SOF_IPC_TYPE_4] = "intel/sof-ipc4-lib/arl-s",
},
.default_tplg_path = {
[SOF_IPC_TYPE_4] = "intel/sof-ace-tplg",
},
.default_fw_filename = {
[SOF_IPC_TYPE_4] = "sof-arl.ri",
[SOF_IPC_TYPE_4] = "sof-arl-s.ri",
},
.nocodec_tplg_filename = "sof-arl-nocodec.tplg",
.ops = &sof_mtl_ops,
@ -83,7 +83,7 @@ static const struct sof_dev_desc arl_desc = {
/* PCI IDs */
static const struct pci_device_id sof_pci_ids[] = {
{ PCI_DEVICE_DATA(INTEL, HDA_MTL, &mtl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_ARL_S, &arl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_ARL_S, &arl_s_desc) },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, sof_pci_ids);