ath10k: add bus type check in ath10k_init_hw_params
The bus type is used together with the other hw parameters to find a matching entry in ath10k_hw_params_list for the device. This is necessary since HL devices can have the same dev_id and target_version as a corresponding LL device (same chipset) and yet use a totally different configuration. Signed-off-by: Erik Stromdahl <erik.stromdahl@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
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7c2dd6154f
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367c899f62
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@ -64,6 +64,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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{
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{
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.id = QCA988X_HW_2_0_VERSION,
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.id = QCA988X_HW_2_0_VERSION,
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.dev_id = QCA988X_2_0_DEVICE_ID,
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.dev_id = QCA988X_2_0_DEVICE_ID,
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.bus = ATH10K_BUS_PCI,
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.name = "qca988x hw2.0",
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.name = "qca988x hw2.0",
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.patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
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.patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
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.uart_pin = 7,
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.uart_pin = 7,
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@ -133,6 +134,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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{
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{
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.id = QCA9887_HW_1_0_VERSION,
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.id = QCA9887_HW_1_0_VERSION,
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.dev_id = QCA9887_1_0_DEVICE_ID,
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.dev_id = QCA9887_1_0_DEVICE_ID,
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.bus = ATH10K_BUS_PCI,
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.name = "qca9887 hw1.0",
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.name = "qca9887 hw1.0",
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.patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR,
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.patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR,
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.uart_pin = 7,
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.uart_pin = 7,
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@ -168,6 +170,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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{
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{
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.id = QCA6174_HW_2_1_VERSION,
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.id = QCA6174_HW_2_1_VERSION,
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.dev_id = QCA6164_2_1_DEVICE_ID,
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.dev_id = QCA6164_2_1_DEVICE_ID,
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.bus = ATH10K_BUS_PCI,
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.name = "qca6164 hw2.1",
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.name = "qca6164 hw2.1",
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.patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
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.patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
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.uart_pin = 6,
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.uart_pin = 6,
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@ -202,6 +205,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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{
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{
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.id = QCA6174_HW_2_1_VERSION,
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.id = QCA6174_HW_2_1_VERSION,
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.dev_id = QCA6174_2_1_DEVICE_ID,
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.dev_id = QCA6174_2_1_DEVICE_ID,
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.bus = ATH10K_BUS_PCI,
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.name = "qca6174 hw2.1",
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.name = "qca6174 hw2.1",
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.patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
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.patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
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.uart_pin = 6,
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.uart_pin = 6,
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@ -236,6 +240,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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{
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{
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.id = QCA6174_HW_3_0_VERSION,
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.id = QCA6174_HW_3_0_VERSION,
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.dev_id = QCA6174_2_1_DEVICE_ID,
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.dev_id = QCA6174_2_1_DEVICE_ID,
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.bus = ATH10K_BUS_PCI,
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.name = "qca6174 hw3.0",
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.name = "qca6174 hw3.0",
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.patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
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.patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
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.uart_pin = 6,
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.uart_pin = 6,
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@ -270,6 +275,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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{
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{
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.id = QCA6174_HW_3_2_VERSION,
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.id = QCA6174_HW_3_2_VERSION,
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.dev_id = QCA6174_2_1_DEVICE_ID,
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.dev_id = QCA6174_2_1_DEVICE_ID,
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.bus = ATH10K_BUS_PCI,
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.name = "qca6174 hw3.2",
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.name = "qca6174 hw3.2",
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.patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
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.patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
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.uart_pin = 6,
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.uart_pin = 6,
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@ -307,6 +313,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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{
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{
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.id = QCA99X0_HW_2_0_DEV_VERSION,
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.id = QCA99X0_HW_2_0_DEV_VERSION,
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.dev_id = QCA99X0_2_0_DEVICE_ID,
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.dev_id = QCA99X0_2_0_DEVICE_ID,
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.bus = ATH10K_BUS_PCI,
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.name = "qca99x0 hw2.0",
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.name = "qca99x0 hw2.0",
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.patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR,
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.patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR,
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.uart_pin = 7,
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.uart_pin = 7,
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@ -347,6 +354,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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{
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{
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.id = QCA9984_HW_1_0_DEV_VERSION,
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.id = QCA9984_HW_1_0_DEV_VERSION,
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.dev_id = QCA9984_1_0_DEVICE_ID,
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.dev_id = QCA9984_1_0_DEVICE_ID,
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.bus = ATH10K_BUS_PCI,
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.name = "qca9984/qca9994 hw1.0",
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.name = "qca9984/qca9994 hw1.0",
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.patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR,
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.patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR,
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.uart_pin = 7,
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.uart_pin = 7,
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@ -394,6 +402,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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{
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{
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.id = QCA9888_HW_2_0_DEV_VERSION,
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.id = QCA9888_HW_2_0_DEV_VERSION,
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.dev_id = QCA9888_2_0_DEVICE_ID,
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.dev_id = QCA9888_2_0_DEVICE_ID,
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.bus = ATH10K_BUS_PCI,
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.name = "qca9888 hw2.0",
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.name = "qca9888 hw2.0",
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.patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR,
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.patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR,
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.uart_pin = 7,
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.uart_pin = 7,
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@ -438,6 +447,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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{
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{
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.id = QCA9377_HW_1_0_DEV_VERSION,
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.id = QCA9377_HW_1_0_DEV_VERSION,
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.dev_id = QCA9377_1_0_DEVICE_ID,
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.dev_id = QCA9377_1_0_DEVICE_ID,
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.bus = ATH10K_BUS_PCI,
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.name = "qca9377 hw1.0",
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.name = "qca9377 hw1.0",
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.patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
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.patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
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.uart_pin = 6,
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.uart_pin = 6,
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@ -472,6 +482,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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{
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{
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.id = QCA9377_HW_1_1_DEV_VERSION,
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.id = QCA9377_HW_1_1_DEV_VERSION,
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.dev_id = QCA9377_1_0_DEVICE_ID,
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.dev_id = QCA9377_1_0_DEVICE_ID,
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.bus = ATH10K_BUS_PCI,
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.name = "qca9377 hw1.1",
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.name = "qca9377 hw1.1",
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.patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
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.patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
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.uart_pin = 6,
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.uart_pin = 6,
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@ -508,6 +519,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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{
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{
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.id = QCA4019_HW_1_0_DEV_VERSION,
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.id = QCA4019_HW_1_0_DEV_VERSION,
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.dev_id = 0,
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.dev_id = 0,
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.bus = ATH10K_BUS_AHB,
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.name = "qca4019 hw1.0",
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.name = "qca4019 hw1.0",
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.patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR,
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.patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR,
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.uart_pin = 7,
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.uart_pin = 7,
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@ -549,6 +561,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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{
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{
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.id = WCN3990_HW_1_0_DEV_VERSION,
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.id = WCN3990_HW_1_0_DEV_VERSION,
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.dev_id = 0,
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.dev_id = 0,
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.bus = ATH10K_BUS_PCI,
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.name = "wcn3990 hw1.0",
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.name = "wcn3990 hw1.0",
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.continuous_frag_desc = true,
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.continuous_frag_desc = true,
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.tx_chain_mask = 0x7,
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.tx_chain_mask = 0x7,
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@ -2085,7 +2098,8 @@ static int ath10k_init_hw_params(struct ath10k *ar)
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for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) {
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for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) {
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hw_params = &ath10k_hw_params_list[i];
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hw_params = &ath10k_hw_params_list[i];
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if (hw_params->id == ar->target_version &&
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if (hw_params->bus == ar->hif.bus &&
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hw_params->id == ar->target_version &&
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hw_params->dev_id == ar->dev_id)
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hw_params->dev_id == ar->dev_id)
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break;
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break;
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}
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}
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@ -92,14 +92,6 @@
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struct ath10k;
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struct ath10k;
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enum ath10k_bus {
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ATH10K_BUS_PCI,
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ATH10K_BUS_AHB,
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ATH10K_BUS_SDIO,
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ATH10K_BUS_USB,
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ATH10K_BUS_SNOC,
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};
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static inline const char *ath10k_bus_str(enum ath10k_bus bus)
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static inline const char *ath10k_bus_str(enum ath10k_bus bus)
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{
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{
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switch (bus) {
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switch (bus) {
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@ -21,6 +21,14 @@
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#include "targaddrs.h"
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#include "targaddrs.h"
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enum ath10k_bus {
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ATH10K_BUS_PCI,
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ATH10K_BUS_AHB,
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ATH10K_BUS_SDIO,
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ATH10K_BUS_USB,
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ATH10K_BUS_SNOC,
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};
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#define ATH10K_FW_DIR "ath10k"
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#define ATH10K_FW_DIR "ath10k"
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#define QCA988X_2_0_DEVICE_ID_UBNT (0x11ac)
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#define QCA988X_2_0_DEVICE_ID_UBNT (0x11ac)
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@ -508,6 +516,7 @@ struct ath10k_hw_clk_params {
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struct ath10k_hw_params {
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struct ath10k_hw_params {
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u32 id;
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u32 id;
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u16 dev_id;
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u16 dev_id;
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enum ath10k_bus bus;
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const char *name;
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const char *name;
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u32 patch_load_addr;
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u32 patch_load_addr;
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int uart_pin;
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int uart_pin;
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