LoongArch: add iommu support
Upstream: no Added iommu support for loongarch Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
This commit is contained in:
Xianglai Li
parent
013ea94d74
commit
364b05f0da
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@ -2200,3 +2200,6 @@ CONFIG_RCU_CPU_STALL_TIMEOUT=60
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# CONFIG_RCU_TRACE is not set
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# CONFIG_STRICT_DEVMEM is not set
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# CONFIG_RUNTIME_TESTING_MENU is not set
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CONFIG_LOONGARCH_IOMMU=m
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CONFIG_CMDLINE_EXTEND=y
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CONFIG_CMDLINE="vfio_iommu_type1.allow_unsafe_interrupts=1 nokaslr"
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@ -0,0 +1,36 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Arch specific extensions to struct device
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*
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* This file is released under the GPLv2
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* Copyright (C) 2020 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_LOONGARCH_DEVICE_H
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#define _ASM_LOONGARCH_DEVICE_H
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struct dev_archdata {
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/* hook for IOMMU specific extension */
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void *iommu;
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struct bus_dma_region *dma_range_map;
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/*
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* On some old 7A chipset, dma address is different from physical
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* address, the main difference is that node id. For dma address
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* node id starts from bit 36, physical node id starts from
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* bit 44. The remaining address below node id is the same.
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*/
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unsigned long dma_node_mask;
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unsigned int dma_node_off;
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};
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struct pdev_archdata {
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};
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struct dma_domain {
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struct list_head node;
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const struct dma_map_ops *dma_ops;
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int domain_nr;
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};
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void add_dma_domain(struct dma_domain *domain);
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void del_dma_domain(struct dma_domain *domain);
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#endif /* _ASM_LOONGARCH_DEVICE_H*/
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@ -35,6 +35,7 @@ config KVM
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select SCHED_INFO
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select MMU_NOTIFIER
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select PREEMPT_NOTIFIERS
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select KVM_VFIO
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help
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Support hosting virtualized guest machines using
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hardware virtualization extensions. You will need
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@ -150,7 +150,7 @@ config OF_IOMMU
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# IOMMU-agnostic DMA-mapping layer
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config IOMMU_DMA
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def_bool ARM64 || IA64 || X86
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def_bool ARM64 || IA64 || X86 || LOONGARCH
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select DMA_OPS
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select IOMMU_API
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select IOMMU_IOVA
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@ -498,4 +498,17 @@ config SPRD_IOMMU
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Say Y here if you want to use the multimedia devices listed above.
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# LOONGARCH IOMMU support
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config LOONGARCH_IOMMU
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tristate "LOONGARCH IOMMU support"
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select IOMMU_API
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select IOMMU_DEFAULT_PASSTHROUGH
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depends on LOONGARCH
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help
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With this option you can enable support for LOONGARCH IOMMU hardware in
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your system. An IOMMU is a hardware component which provides
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remapping of DMA memory accesses from devices. With an LOONGARCH IOMMU you
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can isolate the DMA memory of different devices and protect the
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system from misbehaving device drivers or hardware.
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endif # IOMMU_SUPPORT
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@ -30,3 +30,4 @@ obj-$(CONFIG_VIRTIO_IOMMU) += virtio-iommu.o
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obj-$(CONFIG_IOMMU_SVA) += iommu-sva.o io-pgfault.o
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obj-$(CONFIG_SPRD_IOMMU) += sprd-iommu.o
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obj-$(CONFIG_APPLE_DART) += apple-dart.o
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obj-$(CONFIG_LOONGARCH_IOMMU) += loongarch_iommu.o
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@ -1743,7 +1743,7 @@ static size_t iommu_dma_max_mapping_size(struct device *dev)
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return SIZE_MAX;
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}
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static const struct dma_map_ops iommu_dma_ops = {
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static const struct dma_map_ops iommu_dmafops = {
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.flags = DMA_F_PCI_P2PDMA_SUPPORTED,
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.alloc = iommu_dma_alloc,
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.free = iommu_dma_free,
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@ -1786,7 +1786,7 @@ void iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 dma_limit)
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if (iommu_is_dma_domain(domain)) {
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if (iommu_dma_init_domain(domain, dma_base, dma_limit, dev))
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goto out_err;
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dev->dma_ops = &iommu_dma_ops;
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dev->dma_ops = &iommu_dmafops;
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}
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return;
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,184 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Loongson IOMMU Driver
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*
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* Copyright (C) 2020-2021 Loongson Technology Ltd.
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* Author: Lv Chen <lvchen@loongson.cn>
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* Wang Yang <wangyang@loongson.cn>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef LOONGARCH_IOMMU_H
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#define LOONGARCH_IOMMU_H
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/list.h>
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#include <linux/spinlock.h>
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#include <linux/iommu.h>
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#include <linux/sizes.h>
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#include <asm/addrspace.h>
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#include <linux/io.h>
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#define IOVA_WIDTH 47
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/* Bit value definition for I/O PTE fields */
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#define IOMMU_PTE_PR (1ULL << 0) /* Present */
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#define IOMMU_PTE_HP (1ULL << 1) /* HugePage */
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#define IOMMU_PTE_IR (1ULL << 2) /* Readable */
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#define IOMMU_PTE_IW (1ULL << 3) /* Writeable */
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#define IOMMU_PTE_RW (IOMMU_PTE_PR | IOMMU_PTE_IR | IOMMU_PTE_IW)
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#define iommu_pte_present(ptep) ((*ptep != 0))
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#define iommu_pte_huge(ptep) ((*ptep) & IOMMU_PTE_HP)
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#define LA_IOMMU_PGSIZE (SZ_16K | SZ_32M)
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#define IOMMU_PT_LEVEL0 0x00
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#define IOMMU_PT_LEVEL1 0x01
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/* IOMMU page table */
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#define IOMMU_PAGE_SHIFT PAGE_SHIFT
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#define IOMMU_PAGE_SIZE (_AC(1, UL) << IOMMU_PAGE_SHIFT)
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#define IOMMU_LEVEL_STRIDE (IOMMU_PAGE_SHIFT - 3)
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#define IOMMU_PTRS_PER_LEVEL (IOMMU_PAGE_SIZE >> 3)
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#define IOMMU_LEVEL_SHIFT(n) (((n) * IOMMU_LEVEL_STRIDE) + IOMMU_PAGE_SHIFT)
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#define IOMMU_LEVEL_SIZE(n) (_AC(1, UL) << (((n) * IOMMU_LEVEL_STRIDE) + IOMMU_PAGE_SHIFT))
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#define IOMMU_LEVEL_MASK(n) (~(IOMMU_LEVEL_SIZE(n) - 1))
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#define IOMMU_LEVEL_MAX DIV_ROUND_UP((IOVA_WIDTH - IOMMU_PAGE_SHIFT), IOMMU_LEVEL_STRIDE)
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#define IOMMU_PAGE_MASK (~(IOMMU_PAGE_SIZE - 1))
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#define IOMMU_HPAGE_SIZE (1UL << IOMMU_LEVEL_SHIFT(IOMMU_PT_LEVEL1))
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#define IOMMU_HPAGE_MASK (~(IOMMU_HPAGE_SIZE - 1))
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/* wired | index | domain | shift */
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#define LA_IOMMU_WIDS 0x10
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/* valid | busy | tlbar/aw | cmd */
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#define LA_IOMMU_VBTC 0x14
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#define IOMMU_PGTABLE_BUSY (1 << 16)
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/* enable |index | valid | domain | bdf */
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#define LA_IOMMU_EIVDB 0x18
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/* enable | valid | cmd */
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#define LA_IOMMU_CMD 0x1C
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#define LA_IOMMU_PGD0_LO 0x20
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#define LA_IOMMU_PGD0_HI 0x24
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#define STEP_PGD 0x8
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#define STEP_PGD_SHIFT 3
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#define LA_IOMMU_PGD_LO(domain_id) \
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(LA_IOMMU_PGD0_LO + ((domain_id) << STEP_PGD_SHIFT))
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#define LA_IOMMU_PGD_HI(domain_id) \
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(LA_IOMMU_PGD0_HI + ((domain_id) << STEP_PGD_SHIFT))
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#define LA_IOMMU_DIR_CTRL0 0xA0
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#define LA_IOMMU_DIR_CTRL1 0xA4
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#define LA_IOMMU_DIR_CTRL(x) (LA_IOMMU_DIR_CTRL0 + ((x) << 2))
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#define LA_IOMMU_SAFE_BASE_HI 0xE0
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#define LA_IOMMU_SAFE_BASE_LO 0xE4
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#define LA_IOMMU_EX_ADDR_LO 0xE8
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#define LA_IOMMU_EX_ADDR_HI 0xEC
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#define LA_IOMMU_PFM_CNT_EN 0x100
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#define LA_IOMMU_RD_HIT_CNT_0 0x110
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#define LA_IOMMU_RD_MISS_CNT_O 0x114
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#define LA_IOMMU_WR_HIT_CNT_0 0x118
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#define LA_IOMMU_WR_MISS_CNT_0 0x11C
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#define LA_IOMMU_RD_HIT_CNT_1 0x120
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#define LA_IOMMU_RD_MISS_CNT_1 0x124
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#define LA_IOMMU_WR_HIT_CNT_1 0x128
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#define LA_IOMMU_WR_MISS_CNT_1 0x12C
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#define LA_IOMMU_RD_HIT_CNT_2 0x130
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#define LA_IOMMU_RD_MISS_CNT_2 0x134
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#define LA_IOMMU_WR_HIT_CNT_2 0x138
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#define LA_IOMMU_WR_MISS_CNT_2 0x13C
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#define MAX_DOMAIN_ID 16
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#define MAX_ATTACHED_DEV_ID 16
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#define iommu_ptable_end(addr, end, level) \
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({ unsigned long __boundary = ((addr) + IOMMU_LEVEL_SIZE(level)) & \
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IOMMU_LEVEL_MASK(level); \
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(__boundary - 1 < (end) - 1) ? __boundary : (end); \
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})
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/* To find an entry in an iommu page table directory */
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#define iommu_page_index(addr, level) \
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(((addr) >> ((level * IOMMU_LEVEL_STRIDE) + IOMMU_PAGE_SHIFT)) \
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& (IOMMU_PTRS_PER_LEVEL - 1))
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struct loongarch_iommu {
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struct list_head list; /* for la_iommu_list */
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spinlock_t domain_bitmap_lock; /* Lock for domain allocing */
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spinlock_t dom_info_lock; /* Lock for dom_list */
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void *domain_bitmap; /* Bitmap of global domains */
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void *devtable_bitmap; /* Bitmap of devtable */
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struct list_head dom_list; /* List of all domain privates */
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/* PCI device id of the IOMMU device */
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u16 devid;
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int segment; /* PCI segment# */
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/* iommu configures the register space base address */
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void *confbase;
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/* iommu configures the register space physical base address */
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resource_size_t confbase_phy;
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/* iommu configures the register space size */
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resource_size_t conf_size;
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struct pci_dev *pdev;
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/* Handle for IOMMU core code */
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struct iommu_device iommu_dev;
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} loongarch_iommu;
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struct iommu_rlookup_entry {
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struct list_head list;
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struct loongarch_iommu **rlookup_table;
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int pcisegment;
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};
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struct iommu_info {
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struct list_head list; /* for dom_info->iommu_devlist */
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struct loongarch_iommu *iommu;
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spinlock_t devlock; /* priv dev list lock */
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struct list_head dev_list; /* List of all devices in this domain iommu */
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unsigned int dev_cnt; /* devices assigned to this domain iommu */
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short id;
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} iommu_info;
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/* One vm is equal to a domain,one domain has a priv */
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struct dom_info {
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struct list_head iommu_devlist;
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struct iommu_domain domain;
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struct mutex ptl_lock; /* Lock for page table */
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void *pgd;
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spinlock_t lock; /* Lock for dom_info->iommu_devlist */
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} dom_info;
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struct dom_entry {
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struct list_head list; /* for loongarch_iommu->dom_list */
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struct dom_info *domain_info;
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} dom_entry;
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/* A device for passthrough */
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struct la_iommu_dev_data {
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struct list_head list; /* for iommu_entry->dev_list */
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struct loongarch_iommu *iommu;
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struct iommu_info *iommu_entry;
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struct iommu_domain *domain;
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struct device *dev;
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unsigned short bdf;
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int count;
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int index; /* index in device table */
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};
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static inline unsigned long *iommu_pte_offset(unsigned long *ptep, unsigned long addr, int level)
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{
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return ptep + iommu_page_index(addr, level);
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}
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#endif /* LOONGARCH_IOMMU_H */
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@ -4457,6 +4457,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
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quirk_bridge_cavm_thrx2_pcie_root);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
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quirk_bridge_cavm_thrx2_pcie_root);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON, 0x3c09,
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quirk_bridge_cavm_thrx2_pcie_root);
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/*
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* Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
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@ -5177,6 +5179,8 @@ static const struct pci_dev_acs_enabled {
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{ PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs },
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/* Wangxun nics */
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{ PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs },
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{ PCI_VENDOR_ID_LOONGSON, 0x3c09, pci_quirk_xgene_acs},
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{ PCI_VENDOR_ID_LOONGSON, 0x3c19, pci_quirk_xgene_acs},
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{ 0 }
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};
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@ -39,7 +39,7 @@ config VFIO_GROUP
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config VFIO_CONTAINER
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bool "Support for the VFIO container /dev/vfio/vfio"
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select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64)
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select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64 || LOONGARCH)
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depends on VFIO_GROUP
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default y
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help
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