clk: sunxi-ng: Add support for the D1 SoC clocks
The D1 SoC contains a CCU and a R_CCU (PRCM CCU). Add support for them. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211119043545.4010-7-samuel@sholland.org
This commit is contained in:
Samuel Holland
Maxime Ripard
parent
b30fc68e6c
commit
35b97bb941
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@ -12,6 +12,16 @@ config SUNIV_F1C100S_CCU
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default MACH_SUNIV
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depends on MACH_SUNIV || COMPILE_TEST
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config SUN20I_D1_CCU
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tristate "Support for the Allwinner D1 CCU"
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default RISCV && ARCH_SUNXI
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depends on (RISCV && ARCH_SUNXI) || COMPILE_TEST
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config SUN20I_D1_R_CCU
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tristate "Support for the Allwinner D1 PRCM CCU"
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default RISCV && ARCH_SUNXI
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depends on (RISCV && ARCH_SUNXI) || COMPILE_TEST
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config SUN50I_A64_CCU
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tristate "Support for the Allwinner A64 CCU"
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default ARM64 && ARCH_SUNXI
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@ -25,6 +25,8 @@ sunxi-ccu-y += ccu_mp.o
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# SoC support
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obj-$(CONFIG_SUNIV_F1C100S_CCU) += suniv-f1c100s-ccu.o
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obj-$(CONFIG_SUN20I_D1_CCU) += sun20i-d1-ccu.o
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obj-$(CONFIG_SUN20I_D1_R_CCU) += sun20i-d1-r-ccu.o
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obj-$(CONFIG_SUN50I_A64_CCU) += sun50i-a64-ccu.o
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obj-$(CONFIG_SUN50I_A100_CCU) += sun50i-a100-ccu.o
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obj-$(CONFIG_SUN50I_A100_R_CCU) += sun50i-a100-r-ccu.o
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@ -47,6 +49,8 @@ obj-$(CONFIG_SUN9I_A80_CCU) += sun9i-a80-de-ccu.o
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obj-$(CONFIG_SUN9I_A80_CCU) += sun9i-a80-usb-ccu.o
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suniv-f1c100s-ccu-y += ccu-suniv-f1c100s.o
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sun20i-d1-ccu-y += ccu-sun20i-d1.o
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sun20i-d1-r-ccu-y += ccu-sun20i-d1-r.o
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sun50i-a64-ccu-y += ccu-sun50i-a64.o
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sun50i-a100-ccu-y += ccu-sun50i-a100.o
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sun50i-a100-r-ccu-y += ccu-sun50i-a100-r.o
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@ -0,0 +1,140 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 huangzhenwei@allwinnertech.com
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* Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include "ccu_common.h"
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#include "ccu_reset.h"
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#include "ccu_gate.h"
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#include "ccu_mp.h"
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#include "ccu-sun20i-d1-r.h"
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static const struct clk_parent_data r_ahb_apb0_parents[] = {
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{ .fw_name = "hosc" },
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{ .fw_name = "losc" },
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{ .fw_name = "iosc" },
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{ .fw_name = "pll-periph" },
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};
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static SUNXI_CCU_MP_DATA_WITH_MUX(r_ahb_clk, "r-ahb",
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r_ahb_apb0_parents, 0x000,
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0, 5, /* M */
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8, 2, /* P */
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24, 3, /* mux */
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0);
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static const struct clk_hw *r_ahb_hw = &r_ahb_clk.common.hw;
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static SUNXI_CCU_MP_DATA_WITH_MUX(r_apb0_clk, "r-apb0",
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r_ahb_apb0_parents, 0x00c,
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0, 5, /* M */
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8, 2, /* P */
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24, 3, /* mux */
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0);
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static const struct clk_hw *r_apb0_hw = &r_apb0_clk.common.hw;
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static SUNXI_CCU_GATE_HWS(bus_r_timer_clk, "bus-r-timer", &r_apb0_hw,
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0x11c, BIT(0), 0);
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static SUNXI_CCU_GATE_HWS(bus_r_twd_clk, "bus-r-twd", &r_apb0_hw,
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0x12c, BIT(0), 0);
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static SUNXI_CCU_GATE_HWS(bus_r_ppu_clk, "bus-r-ppu", &r_apb0_hw,
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0x1ac, BIT(0), 0);
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static const struct clk_parent_data r_ir_rx_parents[] = {
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{ .fw_name = "losc" },
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{ .fw_name = "hosc" },
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};
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static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_ir_rx_clk, "r-ir-rx",
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r_ir_rx_parents, 0x1c0,
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0, 5, /* M */
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8, 2, /* P */
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24, 2, /* mux */
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BIT(31), /* gate */
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0);
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static SUNXI_CCU_GATE_HWS(bus_r_ir_rx_clk, "bus-r-ir-rx", &r_apb0_hw,
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0x1cc, BIT(0), 0);
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static SUNXI_CCU_GATE_HWS(bus_r_rtc_clk, "bus-r-rtc", &r_ahb_hw,
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0x20c, BIT(0), 0);
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static SUNXI_CCU_GATE_HWS(bus_r_cpucfg_clk, "bus-r-cpucfg", &r_apb0_hw,
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0x22c, BIT(0), 0);
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static struct ccu_common *sun20i_d1_r_ccu_clks[] = {
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&r_ahb_clk.common,
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&r_apb0_clk.common,
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&bus_r_timer_clk.common,
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&bus_r_twd_clk.common,
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&bus_r_ppu_clk.common,
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&r_ir_rx_clk.common,
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&bus_r_ir_rx_clk.common,
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&bus_r_rtc_clk.common,
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&bus_r_cpucfg_clk.common,
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};
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static struct clk_hw_onecell_data sun20i_d1_r_hw_clks = {
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.num = CLK_NUMBER,
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.hws = {
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[CLK_R_AHB] = &r_ahb_clk.common.hw,
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[CLK_R_APB0] = &r_apb0_clk.common.hw,
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[CLK_BUS_R_TIMER] = &bus_r_timer_clk.common.hw,
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[CLK_BUS_R_TWD] = &bus_r_twd_clk.common.hw,
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[CLK_BUS_R_PPU] = &bus_r_ppu_clk.common.hw,
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[CLK_R_IR_RX] = &r_ir_rx_clk.common.hw,
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[CLK_BUS_R_IR_RX] = &bus_r_ir_rx_clk.common.hw,
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[CLK_BUS_R_RTC] = &bus_r_rtc_clk.common.hw,
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[CLK_BUS_R_CPUCFG] = &bus_r_cpucfg_clk.common.hw,
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},
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};
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static struct ccu_reset_map sun20i_d1_r_ccu_resets[] = {
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[RST_BUS_R_TIMER] = { 0x11c, BIT(16) },
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[RST_BUS_R_TWD] = { 0x12c, BIT(16) },
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[RST_BUS_R_PPU] = { 0x1ac, BIT(16) },
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[RST_BUS_R_IR_RX] = { 0x1cc, BIT(16) },
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[RST_BUS_R_RTC] = { 0x20c, BIT(16) },
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[RST_BUS_R_CPUCFG] = { 0x22c, BIT(16) },
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};
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static const struct sunxi_ccu_desc sun20i_d1_r_ccu_desc = {
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.ccu_clks = sun20i_d1_r_ccu_clks,
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.num_ccu_clks = ARRAY_SIZE(sun20i_d1_r_ccu_clks),
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.hw_clks = &sun20i_d1_r_hw_clks,
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.resets = sun20i_d1_r_ccu_resets,
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.num_resets = ARRAY_SIZE(sun20i_d1_r_ccu_resets),
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};
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static int sun20i_d1_r_ccu_probe(struct platform_device *pdev)
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{
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void __iomem *reg;
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reg = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(reg))
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return PTR_ERR(reg);
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return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun20i_d1_r_ccu_desc);
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}
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static const struct of_device_id sun20i_d1_r_ccu_ids[] = {
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{ .compatible = "allwinner,sun20i-d1-r-ccu" },
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{ }
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};
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static struct platform_driver sun20i_d1_r_ccu_driver = {
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.probe = sun20i_d1_r_ccu_probe,
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.driver = {
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.name = "sun20i-d1-r-ccu",
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.suppress_bind_attrs = true,
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.of_match_table = sun20i_d1_r_ccu_ids,
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},
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};
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module_platform_driver(sun20i_d1_r_ccu_driver);
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MODULE_IMPORT_NS(SUNXI_CCU);
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MODULE_LICENSE("GPL");
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@ -0,0 +1,17 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 frank@allwinnertech.com
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* Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
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*/
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#ifndef _CCU_SUN20I_D1_R_H
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#define _CCU_SUN20I_D1_R_H
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#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
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#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
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#define CLK_R_APB0 1
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#define CLK_NUMBER (CLK_BUS_R_CPUCFG + 1)
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#endif /* _CCU_SUN20I_D1_R_H */
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,15 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 frank@allwinnertech.com
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* Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
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*/
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#ifndef _CCU_SUN20I_D1_H_
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#define _CCU_SUN20I_D1_H_
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#include <dt-bindings/clock/sun20i-d1-ccu.h>
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#include <dt-bindings/reset/sun20i-d1-ccu.h>
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#define CLK_NUMBER (CLK_FANOUT2 + 1)
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#endif /* _CCU_SUN20I_D1_H_ */
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