From 5c23f2dc8eeb5a6010cb66119d942361bc8ec833 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Wed, 30 Aug 2017 10:29:12 +0200 Subject: [PATCH 1/8] phy: add sgmii and 10gkr modes to the phy_mode enum This patch adds more generic PHY modes to the phy_mode enum, to allow configuring generic PHYs to the SGMII and/or the 10GKR mode by using the set_mode callback. Signed-off-by: Antoine Tenart Acked-by: Kishon Vijay Abraham I Signed-off-by: David S. Miller --- include/linux/phy/phy.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index 78bb0d7f6b11..e694d4008c4a 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -27,6 +27,8 @@ enum phy_mode { PHY_MODE_USB_HOST, PHY_MODE_USB_DEVICE, PHY_MODE_USB_OTG, + PHY_MODE_SGMII, + PHY_MODE_10GKR, }; /** From d0438bd6aa097e77f50989c849dbe5f8ff0937ce Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Wed, 30 Aug 2017 10:29:13 +0200 Subject: [PATCH 2/8] phy: add the mvebu cp110 comphy driver On the CP110 unit, which can be found on various Marvell platforms such as the 7k and 8k (currently), a comphy (common PHYs) hardware block can be found. This block provides a number of PHYs which can be used in various modes by other controllers (network, SATA ...). These common PHYs must be configured for the controllers using them to work correctly either at boot time, or when the system runs to switch the mode used. This patch adds a driver for this comphy hardware block, providing callbacks for the its PHYs so that consumers can configure the modes used. As of this commit, two modes are supported by the comphy driver: sgmii and 10gkr. Signed-off-by: Antoine Tenart Acked-by: Kishon Vijay Abraham I Signed-off-by: David S. Miller --- drivers/phy/marvell/Kconfig | 11 + drivers/phy/marvell/Makefile | 1 + drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 644 +++++++++++++++++++ 3 files changed, 656 insertions(+) create mode 100644 drivers/phy/marvell/phy-mvebu-cp110-comphy.c diff --git a/drivers/phy/marvell/Kconfig b/drivers/phy/marvell/Kconfig index 048d8893bc2e..68e321225400 100644 --- a/drivers/phy/marvell/Kconfig +++ b/drivers/phy/marvell/Kconfig @@ -21,6 +21,17 @@ config PHY_BERLIN_USB help Enable this to support the USB PHY on Marvell Berlin SoCs. +config PHY_MVEBU_CP110_COMPHY + tristate "Marvell CP110 comphy driver" + depends on ARCH_MVEBU || COMPILE_TEST + depends on OF + select GENERIC_PHY + help + This driver allows to control the comphy, an hardware block providing + shared serdes PHYs on Marvell Armada 7k/8k (in the CP110). Its serdes + lanes can be used by various controllers (Ethernet, sata, usb, + PCIe...). + config PHY_MVEBU_SATA def_bool y depends on ARCH_DOVE || MACH_DOVE || MACH_KIRKWOOD diff --git a/drivers/phy/marvell/Makefile b/drivers/phy/marvell/Makefile index 3fc188f59118..0cf6a7cbaf9f 100644 --- a/drivers/phy/marvell/Makefile +++ b/drivers/phy/marvell/Makefile @@ -1,6 +1,7 @@ obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY) += phy-armada375-usb2.o obj-$(CONFIG_PHY_BERLIN_SATA) += phy-berlin-sata.o obj-$(CONFIG_PHY_BERLIN_USB) += phy-berlin-usb.o +obj-$(CONFIG_PHY_MVEBU_CP110_COMPHY) += phy-mvebu-cp110-comphy.o obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o obj-$(CONFIG_PHY_PXA_28NM_HSIC) += phy-pxa-28nm-hsic.o obj-$(CONFIG_PHY_PXA_28NM_USB2) += phy-pxa-28nm-usb2.o diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c new file mode 100644 index 000000000000..73ebad6634a7 --- /dev/null +++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c @@ -0,0 +1,644 @@ +/* + * Copyright (C) 2017 Marvell + * + * Antoine Tenart + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Relative to priv->base */ +#define MVEBU_COMPHY_SERDES_CFG0(n) (0x0 + (n) * 0x1000) +#define MVEBU_COMPHY_SERDES_CFG0_PU_PLL BIT(1) +#define MVEBU_COMPHY_SERDES_CFG0_GEN_RX(n) ((n) << 3) +#define MVEBU_COMPHY_SERDES_CFG0_GEN_TX(n) ((n) << 7) +#define MVEBU_COMPHY_SERDES_CFG0_PU_RX BIT(11) +#define MVEBU_COMPHY_SERDES_CFG0_PU_TX BIT(12) +#define MVEBU_COMPHY_SERDES_CFG0_HALF_BUS BIT(14) +#define MVEBU_COMPHY_SERDES_CFG1(n) (0x4 + (n) * 0x1000) +#define MVEBU_COMPHY_SERDES_CFG1_RESET BIT(3) +#define MVEBU_COMPHY_SERDES_CFG1_RX_INIT BIT(4) +#define MVEBU_COMPHY_SERDES_CFG1_CORE_RESET BIT(5) +#define MVEBU_COMPHY_SERDES_CFG1_RF_RESET BIT(6) +#define MVEBU_COMPHY_SERDES_CFG2(n) (0x8 + (n) * 0x1000) +#define MVEBU_COMPHY_SERDES_CFG2_DFE_EN BIT(4) +#define MVEBU_COMPHY_SERDES_STATUS0(n) (0x18 + (n) * 0x1000) +#define MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY BIT(2) +#define MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY BIT(3) +#define MVEBU_COMPHY_SERDES_STATUS0_RX_INIT BIT(4) +#define MVEBU_COMPHY_PWRPLL_CTRL(n) (0x804 + (n) * 0x1000) +#define MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(n) ((n) << 0) +#define MVEBU_COMPHY_PWRPLL_PHY_MODE(n) ((n) << 5) +#define MVEBU_COMPHY_IMP_CAL(n) (0x80c + (n) * 0x1000) +#define MVEBU_COMPHY_IMP_CAL_TX_EXT(n) ((n) << 10) +#define MVEBU_COMPHY_IMP_CAL_TX_EXT_EN BIT(15) +#define MVEBU_COMPHY_DFE_RES(n) (0x81c + (n) * 0x1000) +#define MVEBU_COMPHY_DFE_RES_FORCE_GEN_TBL BIT(15) +#define MVEBU_COMPHY_COEF(n) (0x828 + (n) * 0x1000) +#define MVEBU_COMPHY_COEF_DFE_EN BIT(14) +#define MVEBU_COMPHY_COEF_DFE_CTRL BIT(15) +#define MVEBU_COMPHY_GEN1_S0(n) (0x834 + (n) * 0x1000) +#define MVEBU_COMPHY_GEN1_S0_TX_AMP(n) ((n) << 1) +#define MVEBU_COMPHY_GEN1_S0_TX_EMPH(n) ((n) << 7) +#define MVEBU_COMPHY_GEN1_S1(n) (0x838 + (n) * 0x1000) +#define MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(n) ((n) << 0) +#define MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(n) ((n) << 3) +#define MVEBU_COMPHY_GEN1_S1_RX_MUL_FI(n) ((n) << 6) +#define MVEBU_COMPHY_GEN1_S1_RX_MUL_FF(n) ((n) << 8) +#define MVEBU_COMPHY_GEN1_S1_RX_DFE_EN BIT(10) +#define MVEBU_COMPHY_GEN1_S1_RX_DIV(n) ((n) << 11) +#define MVEBU_COMPHY_GEN1_S2(n) (0x8f4 + (n) * 0x1000) +#define MVEBU_COMPHY_GEN1_S2_TX_EMPH(n) ((n) << 0) +#define MVEBU_COMPHY_GEN1_S2_TX_EMPH_EN BIT(4) +#define MVEBU_COMPHY_LOOPBACK(n) (0x88c + (n) * 0x1000) +#define MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(n) ((n) << 1) +#define MVEBU_COMPHY_VDD_CAL0(n) (0x908 + (n) * 0x1000) +#define MVEBU_COMPHY_VDD_CAL0_CONT_MODE BIT(15) +#define MVEBU_COMPHY_EXT_SELV(n) (0x914 + (n) * 0x1000) +#define MVEBU_COMPHY_EXT_SELV_RX_SAMPL(n) ((n) << 5) +#define MVEBU_COMPHY_MISC_CTRL0(n) (0x93c + (n) * 0x1000) +#define MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE BIT(5) +#define MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL BIT(10) +#define MVEBU_COMPHY_RX_CTRL1(n) (0x940 + (n) * 0x1000) +#define MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL BIT(11) +#define MVEBU_COMPHY_RX_CTRL1_CLK8T_EN BIT(12) +#define MVEBU_COMPHY_SPEED_DIV(n) (0x954 + (n) * 0x1000) +#define MVEBU_COMPHY_SPEED_DIV_TX_FORCE BIT(7) +#define MVEBU_SP_CALIB(n) (0x96c + (n) * 0x1000) +#define MVEBU_SP_CALIB_SAMPLER(n) ((n) << 8) +#define MVEBU_SP_CALIB_SAMPLER_EN BIT(12) +#define MVEBU_COMPHY_TX_SLEW_RATE(n) (0x974 + (n) * 0x1000) +#define MVEBU_COMPHY_TX_SLEW_RATE_EMPH(n) ((n) << 5) +#define MVEBU_COMPHY_TX_SLEW_RATE_SLC(n) ((n) << 10) +#define MVEBU_COMPHY_DLT_CTRL(n) (0x984 + (n) * 0x1000) +#define MVEBU_COMPHY_DLT_CTRL_DTL_FLOOP_EN BIT(2) +#define MVEBU_COMPHY_FRAME_DETECT0(n) (0xa14 + (n) * 0x1000) +#define MVEBU_COMPHY_FRAME_DETECT0_PATN(n) ((n) << 7) +#define MVEBU_COMPHY_FRAME_DETECT3(n) (0xa20 + (n) * 0x1000) +#define MVEBU_COMPHY_FRAME_DETECT3_LOST_TIMEOUT_EN BIT(12) +#define MVEBU_COMPHY_DME(n) (0xa28 + (n) * 0x1000) +#define MVEBU_COMPHY_DME_ETH_MODE BIT(7) +#define MVEBU_COMPHY_TRAINING0(n) (0xa68 + (n) * 0x1000) +#define MVEBU_COMPHY_TRAINING0_P2P_HOLD BIT(15) +#define MVEBU_COMPHY_TRAINING5(n) (0xaa4 + (n) * 0x1000) +#define MVEBU_COMPHY_TRAINING5_RX_TIMER(n) ((n) << 0) +#define MVEBU_COMPHY_TX_TRAIN_PRESET(n) (0xb1c + (n) * 0x1000) +#define MVEBU_COMPHY_TX_TRAIN_PRESET_16B_AUTO_EN BIT(8) +#define MVEBU_COMPHY_TX_TRAIN_PRESET_PRBS11 BIT(9) +#define MVEBU_COMPHY_GEN1_S3(n) (0xc40 + (n) * 0x1000) +#define MVEBU_COMPHY_GEN1_S3_FBCK_SEL BIT(9) +#define MVEBU_COMPHY_GEN1_S4(n) (0xc44 + (n) * 0x1000) +#define MVEBU_COMPHY_GEN1_S4_DFE_RES(n) ((n) << 8) +#define MVEBU_COMPHY_TX_PRESET(n) (0xc68 + (n) * 0x1000) +#define MVEBU_COMPHY_TX_PRESET_INDEX(n) ((n) << 0) +#define MVEBU_COMPHY_GEN1_S5(n) (0xd38 + (n) * 0x1000) +#define MVEBU_COMPHY_GEN1_S5_ICP(n) ((n) << 0) + +/* Relative to priv->regmap */ +#define MVEBU_COMPHY_CONF1(n) (0x1000 + (n) * 0x28) +#define MVEBU_COMPHY_CONF1_PWRUP BIT(1) +#define MVEBU_COMPHY_CONF1_USB_PCIE BIT(2) /* 0: Ethernet/SATA */ +#define MVEBU_COMPHY_CONF6(n) (0x1014 + (n) * 0x28) +#define MVEBU_COMPHY_CONF6_40B BIT(18) +#define MVEBU_COMPHY_SELECTOR 0x1140 +#define MVEBU_COMPHY_SELECTOR_PHY(n) ((n) * 0x4) + +#define MVEBU_COMPHY_LANES 6 +#define MVEBU_COMPHY_PORTS 3 + +struct mvebu_comhy_conf { + enum phy_mode mode; + unsigned lane; + unsigned port; + u32 mux; +}; + +#define MVEBU_COMPHY_CONF(_lane, _port, _mode, _mux) \ + { \ + .lane = _lane, \ + .port = _port, \ + .mode = _mode, \ + .mux = _mux, \ + } + +static const struct mvebu_comhy_conf mvebu_comphy_cp110_modes[] = { + /* lane 0 */ + MVEBU_COMPHY_CONF(0, 1, PHY_MODE_SGMII, 0x1), + /* lane 1 */ + MVEBU_COMPHY_CONF(1, 2, PHY_MODE_SGMII, 0x1), + /* lane 2 */ + MVEBU_COMPHY_CONF(2, 0, PHY_MODE_SGMII, 0x1), + MVEBU_COMPHY_CONF(2, 0, PHY_MODE_10GKR, 0x1), + /* lane 3 */ + MVEBU_COMPHY_CONF(3, 1, PHY_MODE_SGMII, 0x2), + /* lane 4 */ + MVEBU_COMPHY_CONF(4, 0, PHY_MODE_SGMII, 0x2), + MVEBU_COMPHY_CONF(4, 0, PHY_MODE_10GKR, 0x2), + MVEBU_COMPHY_CONF(4, 1, PHY_MODE_SGMII, 0x1), + /* lane 5 */ + MVEBU_COMPHY_CONF(5, 2, PHY_MODE_SGMII, 0x1), +}; + +struct mvebu_comphy_priv { + void __iomem *base; + struct regmap *regmap; + struct device *dev; + int modes[MVEBU_COMPHY_LANES]; +}; + +struct mvebu_comphy_lane { + struct mvebu_comphy_priv *priv; + unsigned id; + enum phy_mode mode; + int port; +}; + +static int mvebu_comphy_get_mux(int lane, int port, enum phy_mode mode) +{ + int i, n = ARRAY_SIZE(mvebu_comphy_cp110_modes); + + /* Unused PHY mux value is 0x0 */ + if (mode == PHY_MODE_INVALID) + return 0; + + for (i = 0; i < n; i++) { + if (mvebu_comphy_cp110_modes[i].lane == lane && + mvebu_comphy_cp110_modes[i].port == port && + mvebu_comphy_cp110_modes[i].mode == mode) + break; + } + + if (i == n) + return -EINVAL; + + return mvebu_comphy_cp110_modes[i].mux; +} + +static void mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane, + enum phy_mode mode) +{ + struct mvebu_comphy_priv *priv = lane->priv; + u32 val; + + regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val); + val &= ~MVEBU_COMPHY_CONF1_USB_PCIE; + val |= MVEBU_COMPHY_CONF1_PWRUP; + regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val); + + /* Select baud rates and PLLs */ + val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); + val &= ~(MVEBU_COMPHY_SERDES_CFG0_PU_PLL | + MVEBU_COMPHY_SERDES_CFG0_PU_RX | + MVEBU_COMPHY_SERDES_CFG0_PU_TX | + MVEBU_COMPHY_SERDES_CFG0_HALF_BUS | + MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xf) | + MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xf)); + if (mode == PHY_MODE_10GKR) + val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xe) | + MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xe); + else if (mode == PHY_MODE_SGMII) + val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x6) | + MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0x6) | + MVEBU_COMPHY_SERDES_CFG0_HALF_BUS; + writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); + + /* reset */ + val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); + val &= ~(MVEBU_COMPHY_SERDES_CFG1_RESET | + MVEBU_COMPHY_SERDES_CFG1_CORE_RESET | + MVEBU_COMPHY_SERDES_CFG1_RF_RESET); + writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); + + /* de-assert reset */ + val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); + val |= MVEBU_COMPHY_SERDES_CFG1_RESET | + MVEBU_COMPHY_SERDES_CFG1_CORE_RESET; + writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); + + /* wait until clocks are ready */ + mdelay(1); + + /* exlicitly disable 40B, the bits isn't clear on reset */ + regmap_read(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), &val); + val &= ~MVEBU_COMPHY_CONF6_40B; + regmap_write(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), val); + + /* refclk selection */ + val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); + val &= ~MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL; + if (mode == PHY_MODE_10GKR) + val |= MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE; + writel(val, priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); + + /* power and pll selection */ + val = readl(priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id)); + val &= ~(MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(0x1f) | + MVEBU_COMPHY_PWRPLL_PHY_MODE(0x7)); + val |= MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(0x1) | + MVEBU_COMPHY_PWRPLL_PHY_MODE(0x4); + writel(val, priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id)); + + val = readl(priv->base + MVEBU_COMPHY_LOOPBACK(lane->id)); + val &= ~MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(0x7); + val |= MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(0x1); + writel(val, priv->base + MVEBU_COMPHY_LOOPBACK(lane->id)); +} + +static int mvebu_comphy_init_plls(struct mvebu_comphy_lane *lane, + enum phy_mode mode) +{ + struct mvebu_comphy_priv *priv = lane->priv; + u32 val; + + /* SERDES external config */ + val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); + val |= MVEBU_COMPHY_SERDES_CFG0_PU_PLL | + MVEBU_COMPHY_SERDES_CFG0_PU_RX | + MVEBU_COMPHY_SERDES_CFG0_PU_TX; + writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); + + /* check rx/tx pll */ + readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id), + val, + val & (MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY | + MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY), + 1000, 150000); + if (!(val & (MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY | + MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY))) + return -ETIMEDOUT; + + /* rx init */ + val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); + val |= MVEBU_COMPHY_SERDES_CFG1_RX_INIT; + writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); + + /* check rx */ + readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id), + val, val & MVEBU_COMPHY_SERDES_STATUS0_RX_INIT, + 1000, 10000); + if (!(val & MVEBU_COMPHY_SERDES_STATUS0_RX_INIT)) + return -ETIMEDOUT; + + val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); + val &= ~MVEBU_COMPHY_SERDES_CFG1_RX_INIT; + writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); + + return 0; +} + +static int mvebu_comphy_set_mode_sgmii(struct phy *phy) +{ + struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); + struct mvebu_comphy_priv *priv = lane->priv; + u32 val; + + mvebu_comphy_ethernet_init_reset(lane, PHY_MODE_SGMII); + + val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); + val &= ~MVEBU_COMPHY_RX_CTRL1_CLK8T_EN; + val |= MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL; + writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); + + val = readl(priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id)); + val &= ~MVEBU_COMPHY_DLT_CTRL_DTL_FLOOP_EN; + writel(val, priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id)); + + regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val); + val &= ~MVEBU_COMPHY_CONF1_USB_PCIE; + val |= MVEBU_COMPHY_CONF1_PWRUP; + regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val); + + val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); + val &= ~MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xf); + val |= MVEBU_COMPHY_GEN1_S0_TX_EMPH(0x1); + writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); + + return mvebu_comphy_init_plls(lane, PHY_MODE_SGMII); +} + +static int mvebu_comphy_set_mode_10gkr(struct phy *phy) +{ + struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); + struct mvebu_comphy_priv *priv = lane->priv; + u32 val; + + mvebu_comphy_ethernet_init_reset(lane, PHY_MODE_10GKR); + + val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); + val |= MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL | + MVEBU_COMPHY_RX_CTRL1_CLK8T_EN; + writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); + + val = readl(priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id)); + val |= MVEBU_COMPHY_DLT_CTRL_DTL_FLOOP_EN; + writel(val, priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id)); + + /* Speed divider */ + val = readl(priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id)); + val |= MVEBU_COMPHY_SPEED_DIV_TX_FORCE; + writel(val, priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id)); + + val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id)); + val |= MVEBU_COMPHY_SERDES_CFG2_DFE_EN; + writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id)); + + /* DFE resolution */ + val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); + val |= MVEBU_COMPHY_DFE_RES_FORCE_GEN_TBL; + writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); + + val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); + val &= ~(MVEBU_COMPHY_GEN1_S0_TX_AMP(0x1f) | + MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xf)); + val |= MVEBU_COMPHY_GEN1_S0_TX_AMP(0x1c) | + MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xe); + writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); + + val = readl(priv->base + MVEBU_COMPHY_GEN1_S2(lane->id)); + val &= ~MVEBU_COMPHY_GEN1_S2_TX_EMPH(0xf); + val |= MVEBU_COMPHY_GEN1_S2_TX_EMPH_EN; + writel(val, priv->base + MVEBU_COMPHY_GEN1_S2(lane->id)); + + val = readl(priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id)); + val |= MVEBU_COMPHY_TX_SLEW_RATE_EMPH(0x3) | + MVEBU_COMPHY_TX_SLEW_RATE_SLC(0x3f); + writel(val, priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id)); + + /* Impedance calibration */ + val = readl(priv->base + MVEBU_COMPHY_IMP_CAL(lane->id)); + val &= ~MVEBU_COMPHY_IMP_CAL_TX_EXT(0x1f); + val |= MVEBU_COMPHY_IMP_CAL_TX_EXT(0xe) | + MVEBU_COMPHY_IMP_CAL_TX_EXT_EN; + writel(val, priv->base + MVEBU_COMPHY_IMP_CAL(lane->id)); + + val = readl(priv->base + MVEBU_COMPHY_GEN1_S5(lane->id)); + val &= ~MVEBU_COMPHY_GEN1_S5_ICP(0xf); + writel(val, priv->base + MVEBU_COMPHY_GEN1_S5(lane->id)); + + val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id)); + val &= ~(MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(0x7) | + MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(0x7) | + MVEBU_COMPHY_GEN1_S1_RX_MUL_FI(0x3) | + MVEBU_COMPHY_GEN1_S1_RX_MUL_FF(0x3)); + val |= MVEBU_COMPHY_GEN1_S1_RX_DFE_EN | + MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(0x2) | + MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(0x2) | + MVEBU_COMPHY_GEN1_S1_RX_MUL_FF(0x1) | + MVEBU_COMPHY_GEN1_S1_RX_DIV(0x3); + writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id)); + + val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id)); + val &= ~(MVEBU_COMPHY_COEF_DFE_EN | MVEBU_COMPHY_COEF_DFE_CTRL); + writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id)); + + val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id)); + val &= ~MVEBU_COMPHY_GEN1_S4_DFE_RES(0x3); + val |= MVEBU_COMPHY_GEN1_S4_DFE_RES(0x1); + writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id)); + + val = readl(priv->base + MVEBU_COMPHY_GEN1_S3(lane->id)); + val |= MVEBU_COMPHY_GEN1_S3_FBCK_SEL; + writel(val, priv->base + MVEBU_COMPHY_GEN1_S3(lane->id)); + + /* rx training timer */ + val = readl(priv->base + MVEBU_COMPHY_TRAINING5(lane->id)); + val &= ~MVEBU_COMPHY_TRAINING5_RX_TIMER(0x3ff); + val |= MVEBU_COMPHY_TRAINING5_RX_TIMER(0x13); + writel(val, priv->base + MVEBU_COMPHY_TRAINING5(lane->id)); + + /* tx train peak to peak hold */ + val = readl(priv->base + MVEBU_COMPHY_TRAINING0(lane->id)); + val |= MVEBU_COMPHY_TRAINING0_P2P_HOLD; + writel(val, priv->base + MVEBU_COMPHY_TRAINING0(lane->id)); + + val = readl(priv->base + MVEBU_COMPHY_TX_PRESET(lane->id)); + val &= ~MVEBU_COMPHY_TX_PRESET_INDEX(0xf); + val |= MVEBU_COMPHY_TX_PRESET_INDEX(0x2); /* preset coeff */ + writel(val, priv->base + MVEBU_COMPHY_TX_PRESET(lane->id)); + + val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id)); + val &= ~MVEBU_COMPHY_FRAME_DETECT3_LOST_TIMEOUT_EN; + writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id)); + + val = readl(priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id)); + val |= MVEBU_COMPHY_TX_TRAIN_PRESET_16B_AUTO_EN | + MVEBU_COMPHY_TX_TRAIN_PRESET_PRBS11; + writel(val, priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id)); + + val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id)); + val &= ~MVEBU_COMPHY_FRAME_DETECT0_PATN(0x1ff); + val |= MVEBU_COMPHY_FRAME_DETECT0_PATN(0x88); + writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id)); + + val = readl(priv->base + MVEBU_COMPHY_DME(lane->id)); + val |= MVEBU_COMPHY_DME_ETH_MODE; + writel(val, priv->base + MVEBU_COMPHY_DME(lane->id)); + + val = readl(priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id)); + val |= MVEBU_COMPHY_VDD_CAL0_CONT_MODE; + writel(val, priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id)); + + val = readl(priv->base + MVEBU_SP_CALIB(lane->id)); + val &= ~MVEBU_SP_CALIB_SAMPLER(0x3); + val |= MVEBU_SP_CALIB_SAMPLER(0x3) | + MVEBU_SP_CALIB_SAMPLER_EN; + writel(val, priv->base + MVEBU_SP_CALIB(lane->id)); + val &= ~MVEBU_SP_CALIB_SAMPLER_EN; + writel(val, priv->base + MVEBU_SP_CALIB(lane->id)); + + /* External rx regulator */ + val = readl(priv->base + MVEBU_COMPHY_EXT_SELV(lane->id)); + val &= ~MVEBU_COMPHY_EXT_SELV_RX_SAMPL(0x1f); + val |= MVEBU_COMPHY_EXT_SELV_RX_SAMPL(0x1a); + writel(val, priv->base + MVEBU_COMPHY_EXT_SELV(lane->id)); + + return mvebu_comphy_init_plls(lane, PHY_MODE_10GKR); +} + +static int mvebu_comphy_power_on(struct phy *phy) +{ + struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); + struct mvebu_comphy_priv *priv = lane->priv; + int ret; + u32 mux, val; + + mux = mvebu_comphy_get_mux(lane->id, lane->port, lane->mode); + if (mux < 0) + return -ENOTSUPP; + + regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val); + val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id)); + val |= mux << MVEBU_COMPHY_SELECTOR_PHY(lane->id); + regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val); + + switch (lane->mode) { + case PHY_MODE_SGMII: + ret = mvebu_comphy_set_mode_sgmii(phy); + break; + case PHY_MODE_10GKR: + ret = mvebu_comphy_set_mode_10gkr(phy); + break; + default: + return -ENOTSUPP; + } + + /* digital reset */ + val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); + val |= MVEBU_COMPHY_SERDES_CFG1_RF_RESET; + writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); + + return ret; +} + +static int mvebu_comphy_set_mode(struct phy *phy, enum phy_mode mode) +{ + struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); + + if (mvebu_comphy_get_mux(lane->id, lane->port, mode) < 0) + return -EINVAL; + + lane->mode = mode; + return 0; +} + +static int mvebu_comphy_power_off(struct phy *phy) +{ + struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); + struct mvebu_comphy_priv *priv = lane->priv; + u32 val; + + val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); + val &= ~(MVEBU_COMPHY_SERDES_CFG1_RESET | + MVEBU_COMPHY_SERDES_CFG1_CORE_RESET | + MVEBU_COMPHY_SERDES_CFG1_RF_RESET); + writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); + + regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val); + val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id)); + regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val); + + return 0; +} + +static const struct phy_ops mvebu_comphy_ops = { + .power_on = mvebu_comphy_power_on, + .power_off = mvebu_comphy_power_off, + .set_mode = mvebu_comphy_set_mode, + .owner = THIS_MODULE, +}; + +static struct phy *mvebu_comphy_xlate(struct device *dev, + struct of_phandle_args *args) +{ + struct mvebu_comphy_lane *lane; + struct phy *phy; + + if (WARN_ON(args->args[0] >= MVEBU_COMPHY_PORTS)) + return ERR_PTR(-EINVAL); + + phy = of_phy_simple_xlate(dev, args); + if (IS_ERR(phy)) + return phy; + + lane = phy_get_drvdata(phy); + if (lane->port >= 0) + return ERR_PTR(-EBUSY); + lane->port = args->args[0]; + + return phy; +} + +static int mvebu_comphy_probe(struct platform_device *pdev) +{ + struct mvebu_comphy_priv *priv; + struct phy_provider *provider; + struct device_node *child; + struct resource *res; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = &pdev->dev; + priv->regmap = + syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "marvell,system-controller"); + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->base = devm_ioremap_resource(&pdev->dev, res); + if (!priv->base) + return -ENOMEM; + + for_each_available_child_of_node(pdev->dev.of_node, child) { + struct mvebu_comphy_lane *lane; + struct phy *phy; + int ret; + u32 val; + + ret = of_property_read_u32(child, "reg", &val); + if (ret < 0) { + dev_err(&pdev->dev, "missing 'reg' property (%d)\n", + ret); + continue; + } + + if (val >= MVEBU_COMPHY_LANES) { + dev_err(&pdev->dev, "invalid 'reg' property\n"); + continue; + } + + lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL); + if (!lane) + return -ENOMEM; + + phy = devm_phy_create(&pdev->dev, child, &mvebu_comphy_ops); + if (IS_ERR(phy)) + return PTR_ERR(phy); + + lane->priv = priv; + lane->mode = PHY_MODE_INVALID; + lane->id = val; + lane->port = -1; + phy_set_drvdata(phy, lane); + + /* + * Once all modes are supported in this driver we should call + * mvebu_comphy_power_off(phy) here to avoid relying on the + * bootloader/firmware configuration. + */ + } + + dev_set_drvdata(&pdev->dev, priv); + provider = devm_of_phy_provider_register(&pdev->dev, + mvebu_comphy_xlate); + return PTR_ERR_OR_ZERO(provider); +} + +static const struct of_device_id mvebu_comphy_of_match_table[] = { + { .compatible = "marvell,comphy-cp110" }, + { }, +}; +MODULE_DEVICE_TABLE(of, mvebu_comphy_of_match_table); + +static struct platform_driver mvebu_comphy_driver = { + .probe = mvebu_comphy_probe, + .driver = { + .name = "mvebu-comphy", + .of_match_table = mvebu_comphy_of_match_table, + }, +}; +module_platform_driver(mvebu_comphy_driver); + +MODULE_AUTHOR("Antoine Tenart "); +MODULE_DESCRIPTION("Common PHY driver for mvebu SoCs"); +MODULE_LICENSE("GPL v2"); From 9c2cbd478ee1830670e562a68d74b2336721b202 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Wed, 30 Aug 2017 10:29:14 +0200 Subject: [PATCH 3/8] Documentation/bindings: phy: document the Marvell comphy driver The Marvell Armada 7K/8K SoCs contains an hardware block called COMPHY that provides a number of shared PHYs used by various interfaces in the SoC: network, SATA, PCIe, etc. This Device Tree binding allows to describe this COMPHY hardware block. Signed-off-by: Antoine Tenart Signed-off-by: David S. Miller --- .../bindings/phy/phy-mvebu-comphy.txt | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt diff --git a/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt b/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt new file mode 100644 index 000000000000..bfcf80341657 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt @@ -0,0 +1,43 @@ +mvebu comphy driver +------------------- + +A comphy controller can be found on Marvell Armada 7k/8k on the CP110. It +provides a number of shared PHYs used by various interfaces (network, sata, +usb, PCIe...). + +Required properties: + +- compatible: should be "marvell,comphy-cp110" +- reg: should contain the comphy register location and length. +- marvell,system-controller: should contain a phandle to the + system controller node. +- #address-cells: should be 1. +- #size-cells: should be 0. + +A sub-node is required for each comphy lane provided by the comphy. + +Required properties (child nodes): + +- reg: comphy lane number. +- #phy-cells : from the generic phy bindings, must be 1. Defines the + input port to use for a given comphy lane. + +Example: + + cpm_comphy: phy@120000 { + compatible = "marvell,comphy-cp110"; + reg = <0x120000 0x6000>; + marvell,system-controller = <&cpm_syscon0>; + #address-cells = <1>; + #size-cells = <0>; + + cpm_comphy0: phy@0 { + reg = <0>; + #phy-cells = <1>; + }; + + cpm_comphy1: phy@1 { + reg = <1>; + #phy-cells = <1>; + }; + }; From 542897d987b0d16c4346952f116acb80a8e82a38 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Wed, 30 Aug 2017 10:29:15 +0200 Subject: [PATCH 4/8] net: mvpp2: initialize the comphy On some platforms, the comphy is between the MAC GoP and the PHYs. The mvpp2 driver currently relies on the firmware/bootloader to configure the comphy. As a comphy driver was added to the generic PHY framework, this patch uses it in the mvpp2 driver to configure the comphy at boot time to avoid relying on the bootloader. Signed-off-by: Antoine Tenart Signed-off-by: David S. Miller --- drivers/net/ethernet/marvell/mvpp2.c | 44 +++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c index fea9ae5b70ba..3dc5f644a8e1 100644 --- a/drivers/net/ethernet/marvell/mvpp2.c +++ b/drivers/net/ethernet/marvell/mvpp2.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -861,6 +862,7 @@ struct mvpp2_port { phy_interface_t phy_interface; struct device_node *phy_node; + struct phy *comphy; unsigned int link; unsigned int duplex; unsigned int speed; @@ -4420,6 +4422,32 @@ invalid_conf: return -EINVAL; } +static int mvpp22_comphy_init(struct mvpp2_port *port) +{ + enum phy_mode mode; + int ret; + + if (!port->comphy) + return 0; + + switch (port->phy_interface) { + case PHY_INTERFACE_MODE_SGMII: + mode = PHY_MODE_SGMII; + break; + case PHY_INTERFACE_MODE_10GKR: + mode = PHY_MODE_10GKR; + break; + default: + return -EINVAL; + } + + ret = phy_set_mode(port->comphy, mode); + if (ret) + return ret; + + return phy_power_on(port->comphy); +} + static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port *port) { u32 val; @@ -6404,8 +6432,10 @@ static void mvpp2_start_dev(struct mvpp2_port *port) /* Enable interrupts on all CPUs */ mvpp2_interrupts_enable(port); - if (port->priv->hw_version == MVPP22) + if (port->priv->hw_version == MVPP22) { + mvpp22_comphy_init(port); mvpp22_gop_init(port); + } mvpp2_port_mii_set(port); mvpp2_port_enable(port); @@ -6436,6 +6466,7 @@ static void mvpp2_stop_dev(struct mvpp2_port *port) mvpp2_egress_disable(port); mvpp2_port_disable(port); phy_stop(ndev->phydev); + phy_power_off(port->comphy); } static int mvpp2_check_ringparam_valid(struct net_device *dev, @@ -7242,6 +7273,7 @@ static int mvpp2_port_probe(struct platform_device *pdev, struct mvpp2 *priv) { struct device_node *phy_node; + struct phy *comphy; struct mvpp2_port *port; struct mvpp2_port_pcpu *port_pcpu; struct net_device *dev; @@ -7285,6 +7317,15 @@ static int mvpp2_port_probe(struct platform_device *pdev, goto err_free_netdev; } + comphy = devm_of_phy_get(&pdev->dev, port_node, NULL); + if (IS_ERR(comphy)) { + if (PTR_ERR(comphy) == -EPROBE_DEFER) { + err = -EPROBE_DEFER; + goto err_free_netdev; + } + comphy = NULL; + } + if (of_property_read_u32(port_node, "port-id", &id)) { err = -EINVAL; dev_err(&pdev->dev, "missing port-id value\n"); @@ -7318,6 +7359,7 @@ static int mvpp2_port_probe(struct platform_device *pdev, port->phy_node = phy_node; port->phy_interface = phy_mode; + port->comphy = comphy; if (priv->hw_version == MVPP21) { res = platform_get_resource(pdev, IORESOURCE_MEM, 2 + id); From 968b211c620b567a4d2183beb0516cbd2c73560a Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Wed, 30 Aug 2017 10:29:16 +0200 Subject: [PATCH 5/8] net: mvpp2: simplify the link_event function The link_event function is somewhat complicated. This cosmetic patch simplifies it. Signed-off-by: Antoine Tenart Signed-off-by: David S. Miller --- drivers/net/ethernet/marvell/mvpp2.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c index 3dc5f644a8e1..cacbd881cebd 100644 --- a/drivers/net/ethernet/marvell/mvpp2.c +++ b/drivers/net/ethernet/marvell/mvpp2.c @@ -5740,7 +5740,6 @@ static void mvpp2_link_event(struct net_device *dev) { struct mvpp2_port *port = netdev_priv(dev); struct phy_device *phydev = dev->phydev; - int status_change = 0; u32 val; if (phydev->link) { @@ -5771,16 +5770,8 @@ static void mvpp2_link_event(struct net_device *dev) } if (phydev->link != port->link) { - if (!phydev->link) { - port->duplex = -1; - port->speed = 0; - } - port->link = phydev->link; - status_change = 1; - } - if (status_change) { if (phydev->link) { val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); val |= (MVPP2_GMAC_FORCE_LINK_PASS | @@ -5789,9 +5780,13 @@ static void mvpp2_link_event(struct net_device *dev) mvpp2_egress_enable(port); mvpp2_ingress_enable(port); } else { + port->duplex = -1; + port->speed = 0; + mvpp2_ingress_disable(port); mvpp2_egress_disable(port); } + phy_print_status(phydev); } } From f55744adeee8598a05f0714b8fe9d131865ef060 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Wed, 30 Aug 2017 10:29:17 +0200 Subject: [PATCH 6/8] net: mvpp2: improve the link management function When the link status changes, the phylib calls the link_event function in the mvpp2 driver. Before this patch only the egress/ingress transmit was enabled/disabled. This patch adds more functionality to the link status management code by enabling/disabling the port per-cpu interrupts, and the port itself. The queues are now stopped as well, and the netif carrier helpers are called. Signed-off-by: Antoine Tenart Signed-off-by: David S. Miller --- drivers/net/ethernet/marvell/mvpp2.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c index cacbd881cebd..0fe146f2bc8c 100644 --- a/drivers/net/ethernet/marvell/mvpp2.c +++ b/drivers/net/ethernet/marvell/mvpp2.c @@ -5777,14 +5777,25 @@ static void mvpp2_link_event(struct net_device *dev) val |= (MVPP2_GMAC_FORCE_LINK_PASS | MVPP2_GMAC_FORCE_LINK_DOWN); writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); + + mvpp2_interrupts_enable(port); + mvpp2_port_enable(port); + mvpp2_egress_enable(port); mvpp2_ingress_enable(port); + netif_carrier_on(dev); + netif_tx_wake_all_queues(dev); } else { port->duplex = -1; port->speed = 0; + netif_tx_stop_all_queues(dev); + netif_carrier_off(dev); mvpp2_ingress_disable(port); mvpp2_egress_disable(port); + + mvpp2_port_disable(port); + mvpp2_interrupts_disable(port); } phy_print_status(phydev); From 65a2c09aea8b9b620bbb3e59f68090a2b7151865 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Wed, 30 Aug 2017 10:29:18 +0200 Subject: [PATCH 7/8] net: mvpp2: do not set GMAC autoneg when using XLG MAC When using the XLG MAC, it does not make sense to force the GMAC autoneg parameters. This patch adds checks to only set the GMAC autoneg parameters when needed (i.e. when not using the XLG MAC). Signed-off-by: Antoine Tenart Signed-off-by: David S. Miller --- drivers/net/ethernet/marvell/mvpp2.c | 64 ++++++++++++++++++---------- 1 file changed, 42 insertions(+), 22 deletions(-) diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c index 0fe146f2bc8c..670395235932 100644 --- a/drivers/net/ethernet/marvell/mvpp2.c +++ b/drivers/net/ethernet/marvell/mvpp2.c @@ -5735,6 +5735,37 @@ static irqreturn_t mvpp2_isr(int irq, void *dev_id) return IRQ_HANDLED; } +static void mvpp2_gmac_set_autoneg(struct mvpp2_port *port, + struct phy_device *phydev) +{ + u32 val; + + if (port->phy_interface != PHY_INTERFACE_MODE_RGMII && + port->phy_interface != PHY_INTERFACE_MODE_RGMII_ID && + port->phy_interface != PHY_INTERFACE_MODE_RGMII_RXID && + port->phy_interface != PHY_INTERFACE_MODE_RGMII_TXID && + port->phy_interface != PHY_INTERFACE_MODE_SGMII) + return; + + val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); + val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED | + MVPP2_GMAC_CONFIG_GMII_SPEED | + MVPP2_GMAC_CONFIG_FULL_DUPLEX | + MVPP2_GMAC_AN_SPEED_EN | + MVPP2_GMAC_AN_DUPLEX_EN); + + if (phydev->duplex) + val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX; + + if (phydev->speed == SPEED_1000) + val |= MVPP2_GMAC_CONFIG_GMII_SPEED; + else if (phydev->speed == SPEED_100) + val |= MVPP2_GMAC_CONFIG_MII_SPEED; + + writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); + +} + /* Adjust link */ static void mvpp2_link_event(struct net_device *dev) { @@ -5745,24 +5776,7 @@ static void mvpp2_link_event(struct net_device *dev) if (phydev->link) { if ((port->speed != phydev->speed) || (port->duplex != phydev->duplex)) { - u32 val; - - val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); - val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED | - MVPP2_GMAC_CONFIG_GMII_SPEED | - MVPP2_GMAC_CONFIG_FULL_DUPLEX | - MVPP2_GMAC_AN_SPEED_EN | - MVPP2_GMAC_AN_DUPLEX_EN); - - if (phydev->duplex) - val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX; - - if (phydev->speed == SPEED_1000) - val |= MVPP2_GMAC_CONFIG_GMII_SPEED; - else if (phydev->speed == SPEED_100) - val |= MVPP2_GMAC_CONFIG_MII_SPEED; - - writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); + mvpp2_gmac_set_autoneg(port, phydev); port->duplex = phydev->duplex; port->speed = phydev->speed; @@ -5773,10 +5787,16 @@ static void mvpp2_link_event(struct net_device *dev) port->link = phydev->link; if (phydev->link) { - val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); - val |= (MVPP2_GMAC_FORCE_LINK_PASS | - MVPP2_GMAC_FORCE_LINK_DOWN); - writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); + if (port->phy_interface == PHY_INTERFACE_MODE_RGMII || + port->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || + port->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || + port->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID || + port->phy_interface == PHY_INTERFACE_MODE_SGMII) { + val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); + val |= (MVPP2_GMAC_FORCE_LINK_PASS | + MVPP2_GMAC_FORCE_LINK_DOWN); + writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); + } mvpp2_interrupts_enable(port); mvpp2_port_enable(port); From 89273bc060d8c7a70999736fe15b2fb3326d0da8 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Wed, 30 Aug 2017 10:29:19 +0200 Subject: [PATCH 8/8] net: mvpp2: dynamic reconfiguration of the comphy/GoP/MAC This patch adds logic to reconfigure the comphy/GoP/MAC when the link state is updated at runtime. This is very useful on boards where many link speed are supported: depending on what is negotiated the PPv2 driver will automatically reconfigures the link between the PHY and the MAC. Signed-off-by: Antoine Tenart Signed-off-by: David S. Miller --- drivers/net/ethernet/marvell/mvpp2.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c index 670395235932..358a9de9daa7 100644 --- a/drivers/net/ethernet/marvell/mvpp2.c +++ b/drivers/net/ethernet/marvell/mvpp2.c @@ -5771,9 +5771,28 @@ static void mvpp2_link_event(struct net_device *dev) { struct mvpp2_port *port = netdev_priv(dev); struct phy_device *phydev = dev->phydev; + bool link_reconfigured = false; u32 val; if (phydev->link) { + if (port->phy_interface != phydev->interface && port->comphy) { + /* disable current port for reconfiguration */ + mvpp2_interrupts_disable(port); + netif_carrier_off(port->dev); + mvpp2_port_disable(port); + phy_power_off(port->comphy); + + /* comphy reconfiguration */ + port->phy_interface = phydev->interface; + mvpp22_comphy_init(port); + + /* gop/mac reconfiguration */ + mvpp22_gop_init(port); + mvpp2_port_mii_set(port); + + link_reconfigured = true; + } + if ((port->speed != phydev->speed) || (port->duplex != phydev->duplex)) { mvpp2_gmac_set_autoneg(port, phydev); @@ -5783,7 +5802,7 @@ static void mvpp2_link_event(struct net_device *dev) } } - if (phydev->link != port->link) { + if (phydev->link != port->link || link_reconfigured) { port->link = phydev->link; if (phydev->link) {