soc/tegra: Changes for v4.8-rc1
Contains fixes and cleanups to the PMC driver, as well as some fixes for the generic PM domain support and some prep work to support PCIe on 64- bit ARM. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJXdn7eAAoJEN0jrNd/PrOhDc4P/2U04qs7hhaI94NmrWBDto2O OKHezveursISPEFZ+FebMF5mSNwdBG0RitKm813TwoYDEKk6Dc7GV4nQHwHPVYqW 7xK2VrqU3GpEXXSgGu6dupwx/W6ID/L6gkghg01yVVwuvuNOrCDqWTv5EM++9Ydg 5SPBP2Nvc3CQr/Q71WU8uQueTmtQoQanZC8an/CBzRO2nA8HDBDaXfQ+dgkP/U8l QfM9TJbFgbg9s+gwboL9UwnFmDtNNRDFPEYU8Ij9q+VDW4LEodErrVVO2NSwVhG4 A8KlkUO6N/pHRTjWnERHXUS/kCUM7BRoOum+KjMUdz3SO6iSuZFaKUein7R2fld4 iV+ichP+DpnkdSpPtgTcFYUeGM1QWfBij+9owloCE4k1pr08hS8eYWxReZ9rsVGN 43ZBZg/ia41RhojfNDtAK0ntXhak7t5DIiDpi9OO7pvCtU6aYxZxzFu+C9UiCcZ3 zPHDxHkCVEjbSdrbd6AhkOIbQ9BKk9pab0iya+B3JSJTFensxYkLhAbYkmDgXiPA 8+pySykkmogBJjsiKBbANlz+5c0etMnjTpd9jBzBuagKahfpZndHtCL8VlA2Blhh d7KORcCf1PCEoqALoj0NXhi7IxF9KrbonpQcFspWV4zFSdhBkj5O8wkR10J5q4zG 4iJt7/bmYoWO/dbRTjbr =eFoM -----END PGP SIGNATURE----- Merge tag 'tegra-for-4.8-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers soc/tegra: Changes for v4.8-rc1 Contains fixes and cleanups to the PMC driver, as well as some fixes for the generic PM domain support and some prep work to support PCIe on 64- bit ARM. * tag 'tegra-for-4.8-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: Stub out PCIe IRQ workaround on 64-bit ARM soc/tegra: pmc: Enable XUSB partitions on boot soc/tegra: pmc: Initialise power partitions early soc/tegra: pmc: Add specific error messages soc/tegra: pmc: Use whitespace more consistently soc/tegra: pmc: Don't probe PMC if early initialisation fails soc/tegra: pmc: Add missing of_node_put() soc/tegra: pmc: Ensure mutex is always initialised soc/tegra: pmc: Don't populate SoC data until register space is mapped soc/tegra: pmc: Fix early initialisation of PMC soc/tegra: pmc: Ensure powergate is available when powering on soc/tegra: pmc: Initialise resets associated with a power partition soc/tegra: pmc: Use register definitions instead of magic values Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
358c79174a
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@ -51,6 +51,7 @@
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#define PMC_CNTRL_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */
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#define PMC_CNTRL_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */
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#define PMC_CNTRL_INTR_POLARITY (1 << 17) /* inverts INTR polarity */
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#define PMC_CNTRL_MAIN_RST (1 << 4)
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#define DPD_SAMPLE 0x020
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#define DPD_SAMPLE_ENABLE (1 << 0)
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@ -80,6 +81,14 @@
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#define PMC_SENSOR_CTRL_SCRATCH_WRITE (1 << 2)
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#define PMC_SENSOR_CTRL_ENABLE_RST (1 << 1)
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#define PMC_RST_STATUS 0x1b4
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#define PMC_RST_STATUS_POR 0
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#define PMC_RST_STATUS_WATCHDOG 1
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#define PMC_RST_STATUS_SENSOR 2
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#define PMC_RST_STATUS_SW_MAIN 3
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#define PMC_RST_STATUS_LP0 4
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#define PMC_RST_STATUS_AOTAG 5
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#define IO_DPD_REQ 0x1b8
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#define IO_DPD_REQ_CODE_IDLE (0 << 30)
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#define IO_DPD_REQ_CODE_OFF (1 << 30)
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@ -399,6 +408,7 @@ static int tegra_powergate_power_up(struct tegra_powergate *pg,
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disable_clks:
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tegra_powergate_disable_clocks(pg);
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usleep_range(10, 20);
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powergate_off:
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tegra_powergate_set(pg->id, false);
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@ -436,6 +446,7 @@ assert_resets:
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usleep_range(10, 20);
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tegra_powergate_reset_deassert(pg);
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usleep_range(10, 20);
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disable_clks:
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tegra_powergate_disable_clocks(pg);
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@ -540,6 +551,9 @@ int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
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struct tegra_powergate pg;
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int err;
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if (!tegra_powergate_is_available(id))
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return -EINVAL;
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pg.id = id;
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pg.clks = &clk;
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pg.num_clks = 1;
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@ -638,9 +652,10 @@ static int tegra_pmc_restart_notify(struct notifier_block *this,
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tegra_pmc_writel(value, PMC_SCRATCH0);
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value = tegra_pmc_readl(0);
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value |= 0x10;
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tegra_pmc_writel(value, 0);
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/* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
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value = tegra_pmc_readl(PMC_CNTRL);
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value |= PMC_CNTRL_MAIN_RST;
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tegra_pmc_writel(value, PMC_CNTRL);
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return NOTIFY_DONE;
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}
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@ -722,13 +737,14 @@ static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
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err:
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while (i--)
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clk_put(pg->clks[i]);
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kfree(pg->clks);
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return err;
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}
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static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
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struct device_node *np)
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struct device_node *np, bool off)
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{
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struct reset_control *rst;
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unsigned int i, count;
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@ -748,6 +764,16 @@ static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
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err = PTR_ERR(pg->resets[i]);
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goto error;
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}
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if (off)
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err = reset_control_assert(pg->resets[i]);
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else
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err = reset_control_deassert(pg->resets[i]);
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if (err) {
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reset_control_put(pg->resets[i]);
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goto error;
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}
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}
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pg->num_resets = count;
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@ -757,6 +783,7 @@ static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
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error:
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while (i--)
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reset_control_put(pg->resets[i]);
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kfree(pg->resets);
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return err;
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@ -765,16 +792,19 @@ error:
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static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
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{
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struct tegra_powergate *pg;
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int id, err;
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bool off;
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int id;
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pg = kzalloc(sizeof(*pg), GFP_KERNEL);
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if (!pg)
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goto error;
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return;
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id = tegra_powergate_lookup(pmc, np->name);
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if (id < 0)
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if (id < 0) {
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dev_err(pmc->dev, "powergate lookup failed for %s: %d\n",
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np->name, id);
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goto free_mem;
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}
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/*
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* Clear the bit for this powergate so it cannot be managed
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@ -788,31 +818,64 @@ static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
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pg->genpd.power_on = tegra_genpd_power_on;
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pg->pmc = pmc;
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if (tegra_powergate_of_get_clks(pg, np))
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goto set_available;
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if (tegra_powergate_of_get_resets(pg, np))
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goto remove_clks;
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off = !tegra_powergate_is_powered(pg->id);
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err = tegra_powergate_of_get_clks(pg, np);
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if (err < 0) {
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dev_err(pmc->dev, "failed to get clocks for %s: %d\n",
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np->name, err);
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goto set_available;
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}
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err = tegra_powergate_of_get_resets(pg, np, off);
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if (err < 0) {
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dev_err(pmc->dev, "failed to get resets for %s: %d\n",
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np->name, err);
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goto remove_clks;
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}
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if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS))
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goto power_on_cleanup;
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/*
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* FIXME: If XHCI is enabled for Tegra, then power-up the XUSB
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* host and super-speed partitions. Once the XHCI driver
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* manages the partitions itself this code can be removed. Note
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* that we don't register these partitions with the genpd core
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* to avoid it from powering down the partitions as they appear
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* to be unused.
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*/
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if (IS_ENABLED(CONFIG_USB_XHCI_TEGRA) &&
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(id == TEGRA_POWERGATE_XUSBA || id == TEGRA_POWERGATE_XUSBC))
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goto power_on_cleanup;
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pm_genpd_init(&pg->genpd, NULL, off);
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if (of_genpd_add_provider_simple(np, &pg->genpd))
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err = of_genpd_add_provider_simple(np, &pg->genpd);
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if (err < 0) {
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dev_err(pmc->dev, "failed to add genpd provider for %s: %d\n",
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np->name, err);
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goto remove_resets;
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}
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dev_dbg(pmc->dev, "added power domain %s\n", pg->genpd.name);
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return;
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power_on_cleanup:
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if (off)
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WARN_ON(tegra_powergate_power_up(pg, true));
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remove_resets:
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while (pg->num_resets--)
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reset_control_put(pg->resets[pg->num_resets]);
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kfree(pg->resets);
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remove_clks:
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while (pg->num_clks--)
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clk_put(pg->clks[pg->num_clks]);
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kfree(pg->clks);
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set_available:
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@ -820,16 +883,20 @@ set_available:
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free_mem:
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kfree(pg);
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error:
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dev_err(pmc->dev, "failed to create power domain for %s\n", np->name);
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}
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static void tegra_powergate_init(struct tegra_pmc *pmc)
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static void tegra_powergate_init(struct tegra_pmc *pmc,
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struct device_node *parent)
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{
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struct device_node *np, *child;
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unsigned int i;
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np = of_get_child_by_name(pmc->dev->of_node, "powergates");
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/* Create a bitmap of the available and valid partitions */
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for (i = 0; i < pmc->soc->num_powergates; i++)
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if (pmc->soc->powergates[i])
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set_bit(i, pmc->powergates_available);
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np = of_get_child_by_name(parent, "powergates");
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if (!np)
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return;
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@ -1205,6 +1272,14 @@ static int tegra_pmc_probe(struct platform_device *pdev)
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struct resource *res;
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int err;
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/*
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* Early initialisation should have configured an initial
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* register mapping and setup the soc data pointer. If these
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* are not valid then something went badly wrong!
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*/
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if (WARN_ON(!pmc->base || !pmc->soc))
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return -ENODEV;
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err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
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if (err < 0)
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return err;
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@ -1242,8 +1317,6 @@ static int tegra_pmc_probe(struct platform_device *pdev)
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return err;
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}
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tegra_powergate_init(pmc);
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mutex_lock(&pmc->powergates_lock);
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iounmap(pmc->base);
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pmc->base = base;
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@ -1477,10 +1550,11 @@ static int __init tegra_pmc_early_init(void)
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const struct of_device_id *match;
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struct device_node *np;
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struct resource regs;
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unsigned int i;
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bool invert;
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u32 value;
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mutex_init(&pmc->powergates_lock);
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np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
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if (!np) {
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/*
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@ -1515,39 +1589,40 @@ static int __init tegra_pmc_early_init(void)
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*/
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if (of_address_to_resource(np, 0, ®s) < 0) {
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pr_err("failed to get PMC registers\n");
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of_node_put(np);
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return -ENXIO;
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}
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pmc->soc = match->data;
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}
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pmc->base = ioremap_nocache(regs.start, resource_size(®s));
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if (!pmc->base) {
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pr_err("failed to map PMC registers\n");
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of_node_put(np);
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return -ENXIO;
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}
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/* Create a bit-map of the available and valid partitions */
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for (i = 0; i < pmc->soc->num_powergates; i++)
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if (pmc->soc->powergates[i])
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set_bit(i, pmc->powergates_available);
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if (np) {
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pmc->soc = match->data;
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mutex_init(&pmc->powergates_lock);
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tegra_powergate_init(pmc, np);
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/*
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* Invert the interrupt polarity if a PMC device tree node exists and
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* contains the nvidia,invert-interrupt property.
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*/
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invert = of_property_read_bool(np, "nvidia,invert-interrupt");
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/*
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* Invert the interrupt polarity if a PMC device tree node
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* exists and contains the nvidia,invert-interrupt property.
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*/
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invert = of_property_read_bool(np, "nvidia,invert-interrupt");
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value = tegra_pmc_readl(PMC_CNTRL);
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value = tegra_pmc_readl(PMC_CNTRL);
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if (invert)
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value |= PMC_CNTRL_INTR_POLARITY;
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else
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value &= ~PMC_CNTRL_INTR_POLARITY;
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if (invert)
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value |= PMC_CNTRL_INTR_POLARITY;
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else
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value &= ~PMC_CNTRL_INTR_POLARITY;
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tegra_pmc_writel(value, PMC_CNTRL);
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tegra_pmc_writel(value, PMC_CNTRL);
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of_node_put(np);
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}
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return 0;
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}
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@ -14,7 +14,7 @@
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#ifndef __SOC_TEGRA_CPUIDLE_H__
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#define __SOC_TEGRA_CPUIDLE_H__
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#ifdef CONFIG_CPU_IDLE
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#if defined(CONFIG_ARM) && defined(CONFIG_CPU_IDLE)
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void tegra_cpuidle_pcie_irqs_in_use(void);
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#else
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static inline void tegra_cpuidle_pcie_irqs_in_use(void)
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