mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode
Some controllers, like the cadence qspi controller, have trouble reading only 1 byte in DTR mode. So, do 2 byte reads for SR and FSR commands in DTR mode, and then discard the second byte. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20201005153138.6437-8-p.yadav@ti.com
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@ -370,7 +370,7 @@ int spi_nor_write_disable(struct spi_nor *nor)
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* spi_nor_read_sr() - Read the Status Register.
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* @nor: pointer to 'struct spi_nor'.
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* @sr: pointer to a DMA-able buffer where the value of the
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* Status Register will be written.
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* Status Register will be written. Should be at least 2 bytes.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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@ -388,6 +388,11 @@ static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
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if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
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op.addr.nbytes = nor->params->rdsr_addr_nbytes;
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op.dummy.nbytes = nor->params->rdsr_dummy;
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/*
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* We don't want to read only one byte in DTR mode. So,
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* read 2 and then discard the second byte.
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*/
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op.data.nbytes = 2;
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}
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spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
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@ -408,7 +413,8 @@ static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
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* spi_nor_read_fsr() - Read the Flag Status Register.
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* @nor: pointer to 'struct spi_nor'
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* @fsr: pointer to a DMA-able buffer where the value of the
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* Flag Status Register will be written.
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* Flag Status Register will be written. Should be at least 2
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* bytes.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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@ -426,6 +432,11 @@ static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
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if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
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op.addr.nbytes = nor->params->rdsr_addr_nbytes;
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op.dummy.nbytes = nor->params->rdsr_dummy;
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/*
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* We don't want to read only one byte in DTR mode. So,
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* read 2 and then discard the second byte.
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*/
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op.data.nbytes = 2;
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}
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spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
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