KVM: PPC: Book3S HV P9: Reduce mtmsrd instructions required to save host SPRs
This reduces the number of mtmsrd required to enable facility bits when saving/restoring registers, by having the KVM code set all bits up front rather than using individual facility functions that set their particular MSR bits. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20211123095231.1036501-20-npiggin@gmail.com
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174a3ab633
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@ -112,6 +112,8 @@ static inline void clear_task_ebb(struct task_struct *t)
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#endif
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}
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void kvmppc_save_user_regs(void);
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extern int set_thread_tidr(struct task_struct *t);
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#endif /* _ASM_POWERPC_SWITCH_TO_H */
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@ -1156,6 +1156,34 @@ static inline void save_sprs(struct thread_struct *t)
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#endif
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}
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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void kvmppc_save_user_regs(void)
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{
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unsigned long usermsr;
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if (!current->thread.regs)
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return;
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usermsr = current->thread.regs->msr;
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if (usermsr & MSR_FP)
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save_fpu(current);
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if (usermsr & MSR_VEC)
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save_altivec(current);
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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if (usermsr & MSR_TM) {
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current->thread.tm_tfhar = mfspr(SPRN_TFHAR);
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current->thread.tm_tfiar = mfspr(SPRN_TFIAR);
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current->thread.tm_texasr = mfspr(SPRN_TEXASR);
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current->thread.regs->msr &= ~MSR_TM;
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}
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#endif
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}
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EXPORT_SYMBOL_GPL(kvmppc_save_user_regs);
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#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
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static inline void restore_sprs(struct thread_struct *old_thread,
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struct thread_struct *new_thread)
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{
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@ -4153,6 +4153,7 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
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struct p9_host_os_sprs host_os_sprs;
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s64 dec;
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u64 tb, next_timer;
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unsigned long msr;
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int trap;
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WARN_ON_ONCE(vcpu->arch.ceded);
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@ -4164,8 +4165,23 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
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if (next_timer < time_limit)
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time_limit = next_timer;
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vcpu->arch.ceded = 0;
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save_p9_host_os_sprs(&host_os_sprs);
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/* MSR bits may have been cleared by context switch */
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msr = 0;
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if (IS_ENABLED(CONFIG_PPC_FPU))
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msr |= MSR_FP;
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if (cpu_has_feature(CPU_FTR_ALTIVEC))
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msr |= MSR_VEC;
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if (cpu_has_feature(CPU_FTR_VSX))
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msr |= MSR_VSX;
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if (cpu_has_feature(CPU_FTR_TM) ||
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cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))
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msr |= MSR_TM;
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msr = msr_check_and_set(msr);
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kvmppc_subcore_enter_guest();
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vc->entry_exit_map = 1;
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@ -4174,12 +4190,13 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
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vcpu_vpa_increment_dispatch(vcpu);
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if (cpu_has_feature(CPU_FTR_TM) ||
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cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))
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cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST)) {
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kvmppc_restore_tm_hv(vcpu, vcpu->arch.shregs.msr, true);
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msr = mfmsr(); /* TM restore can update msr */
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}
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switch_pmu_to_guest(vcpu, &host_os_sprs);
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msr_check_and_set(MSR_FP | MSR_VEC | MSR_VSX);
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load_fp_state(&vcpu->arch.fp);
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#ifdef CONFIG_ALTIVEC
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load_vr_state(&vcpu->arch.vr);
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@ -4288,7 +4305,6 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
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restore_p9_host_os_sprs(vcpu, &host_os_sprs);
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msr_check_and_set(MSR_FP | MSR_VEC | MSR_VSX);
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store_fp_state(&vcpu->arch.fp);
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#ifdef CONFIG_ALTIVEC
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store_vr_state(&vcpu->arch.vr);
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@ -4851,19 +4867,24 @@ static int kvmppc_vcpu_run_hv(struct kvm_vcpu *vcpu)
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unsigned long user_tar = 0;
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unsigned int user_vrsave;
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struct kvm *kvm;
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unsigned long msr;
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if (!vcpu->arch.sane) {
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run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
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return -EINVAL;
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}
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/* No need to go into the guest when all we'll do is come back out */
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if (signal_pending(current)) {
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run->exit_reason = KVM_EXIT_INTR;
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return -EINTR;
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}
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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/*
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* Don't allow entry with a suspended transaction, because
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* the guest entry/exit code will lose it.
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* If the guest has TM enabled, save away their TM-related SPRs
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* (they will get restored by the TM unavailable interrupt).
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*/
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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if (cpu_has_feature(CPU_FTR_TM) && current->thread.regs &&
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(current->thread.regs->msr & MSR_TM)) {
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if (MSR_TM_ACTIVE(current->thread.regs->msr)) {
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@ -4871,12 +4892,6 @@ static int kvmppc_vcpu_run_hv(struct kvm_vcpu *vcpu)
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run->fail_entry.hardware_entry_failure_reason = 0;
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return -EINVAL;
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}
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/* Enable TM so we can read the TM SPRs */
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mtmsr(mfmsr() | MSR_TM);
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current->thread.tm_tfhar = mfspr(SPRN_TFHAR);
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current->thread.tm_tfiar = mfspr(SPRN_TFIAR);
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current->thread.tm_texasr = mfspr(SPRN_TEXASR);
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current->thread.regs->msr &= ~MSR_TM;
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}
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#endif
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@ -4891,18 +4906,24 @@ static int kvmppc_vcpu_run_hv(struct kvm_vcpu *vcpu)
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kvmppc_core_prepare_to_enter(vcpu);
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/* No need to go into the guest when all we'll do is come back out */
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if (signal_pending(current)) {
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run->exit_reason = KVM_EXIT_INTR;
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return -EINTR;
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}
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kvm = vcpu->kvm;
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atomic_inc(&kvm->arch.vcpus_running);
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/* Order vcpus_running vs. mmu_ready, see kvmppc_alloc_reset_hpt */
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smp_mb();
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flush_all_to_thread(current);
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msr = 0;
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if (IS_ENABLED(CONFIG_PPC_FPU))
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msr |= MSR_FP;
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if (cpu_has_feature(CPU_FTR_ALTIVEC))
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msr |= MSR_VEC;
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if (cpu_has_feature(CPU_FTR_VSX))
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msr |= MSR_VSX;
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if (cpu_has_feature(CPU_FTR_TM) ||
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cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))
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msr |= MSR_TM;
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msr = msr_check_and_set(msr);
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kvmppc_save_user_regs();
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/* Save userspace EBB and other register values */
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if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
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@ -224,6 +224,7 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpc
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vc->tb_offset_applied = vc->tb_offset;
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}
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/* Could avoid mfmsr by passing around, but probably no big deal */
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msr = mfmsr();
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host_hfscr = mfspr(SPRN_HFSCR);
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