iio: ad7949: fix incorrect SPI xfer len
This driver supports 14-bits and 16-bits devices. All of them have a 14-bit configuration registers. All SPI trasfers, for reading AD conversion results and for writing the configuration register, fit in two bytes. The driver always uses 4-bytes xfers which seems at least pointless (maybe even harmful). This patch trims the SPI xfer len and the buffer size to two bytes. Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Reviewed-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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@ -54,7 +54,7 @@ struct ad7949_adc_chip {
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u8 resolution;
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u16 cfg;
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unsigned int current_channel;
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u32 buffer ____cacheline_aligned;
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u16 buffer ____cacheline_aligned;
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};
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static int ad7949_spi_write_cfg(struct ad7949_adc_chip *ad7949_adc, u16 val,
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@ -67,7 +67,7 @@ static int ad7949_spi_write_cfg(struct ad7949_adc_chip *ad7949_adc, u16 val,
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struct spi_transfer tx[] = {
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{
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.tx_buf = &ad7949_adc->buffer,
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.len = 4,
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.len = 2,
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.bits_per_word = bits_per_word,
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},
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};
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@ -95,7 +95,7 @@ static int ad7949_spi_read_channel(struct ad7949_adc_chip *ad7949_adc, int *val,
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struct spi_transfer tx[] = {
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{
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.rx_buf = &ad7949_adc->buffer,
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.len = 4,
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.len = 2,
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.bits_per_word = bits_per_word,
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},
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};
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